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PIC16CR7X Data Sheet
28/40-Pin, 8-Bit CMOS ROM Microcontrollers
(c) 2007 Microchip Technology Inc.
DS21993C
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS21993C-page ii
(c) 2007 Microchip Technology Inc.
PIC16CR7X
28/40-Pin, 8-Bit CMOS ROM Microcontrollers
Devices Included in this Data Sheet:
* PIC16CR73 * PIC16CR74 * PIC16CR76 * PIC16CR77
Peripheral Features:
* Timer0: 8-bit timer/counter with 8-bit prescaler * Timer1: 16-bit timer/counter with prescaler, can be incremented during Sleep via external crystal/clock * Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler * Two Capture, Compare, PWM modules: - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * 8-bit, up to 8-channel Analog-to-Digital converter * Synchronous Serial Port (SSP) with SPI (Master mode) and I2CTM (Slave) * Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) * Parallel Slave Port (PSP), 8-bits wide with external RD, WR and CS controls (40/44-pin only) * Brown-out detection circuitry for Brown-out Reset (BOR)
High-Performance RISC CPU:
* High-performance RISC CPU * Only 35 single-word instructions to learn * All single-cycle instructions except for program branches which are two-cycle * Operating speed: DC - 20 MHz clock input DC - 200 ns instruction cycle * Up to 8K x 14 words of ROM Program Memory, Up to 368 x 8 bytes of Data Memory (RAM) * Function compatible to the PIC16F73/74/76/77 * Pinout compatible to the PIC16F873/874/876/877 * Interrupt capability (up to 12 sources) * Eight-level deep hardware stack * Direct, Indirect and Relative Addressing modes * Processor read access to program memory
Special Microcontroller Features:
* Power-on Reset (POR) * Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation * Power-Saving Sleep mode * Selectable oscillator options
CMOS Technology:
* * * * * * Low-power, high-speed CMOS ROM technology Fully static design Wide operating voltage range: 2.0V to 5.5V High Sink/Source Current: 25 mA Industrial temperature range Low power consumption: - < 2 mA typical @ 5V, 4 MHz - TBD - 20 A typical @ 3V, 32 kHz - TBD - < 1 A typical standby current - TBD
Device
Program Data Memory SRAM I/O (# Single Word (Bytes) Instructions) 4096 4096 8192 8192 192 192 368 368 22 33 22 33
SSP 8-bit CCP Interrupts A/D (ch) (PWM) 11 12 11 12 5 8 5 8 2 2 2 2 Timers SPI I2CTM USART 8/16-bit (Master) (Slave) Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes 2/1 2/1 2/1 2/1
PIC16CR73 PIC16CR74 PIC16CR76 PIC16CR77
(c) 2007 Microchip Technology Inc.
DS21993C-page 1
PIC16CR7X
Pin Diagrams
PDIP, SOIC, SSOP
MCLR RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA
PIC16CR76/73
RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS VSS OSC1/CLKIN OSC2/CLKOUT
1 2 3 4 5 6 7
28 27 26 25 24 23 22 21 20 PIC16CR73 19 18 PIC16CR76 17 16 15 8 9 10 11 12 13 14
RA1/AN1 RA0/AN0 MCLR RB7 RB6 RB5 RB4
QFN
RB3 RB2 RB1 RB0/INT VDD VSS RC7/RX/DT
PDIP
MCLR RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2
PIC16CR77/74
DS21993C-page 2
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK
(c) 2007 Microchip Technology Inc.
PIC16CR7X
Pin Diagrams (Continued)
PLCC
RA3/AN3/VREF RA2/AN2 RA1/AN1 RA0/AN0 MCLR NC RB7 RB6 RB5 RB4 NC RA4/T0CKI RA5/AN4/SS RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T1OSO/T1CK1 NC 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 9
44 43 42 41 40 39 38 37 36 35 34
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1 RC1/T1OSI/CCP2 NC
TQFP
RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RC4/SDI/SDA RC5/SDO RC6/TX/CK NC
18 19 20 21 22 23 24 25 26 27 282
7 8 9 10 11 12 13 14 15 16 17
PIC16CR77 PIC16CR74
RB3 RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT
(c) 2007 Microchip Technology Inc.
NC NC RB4 RB5 RB6 RB7 MCLR RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF
12 13 14 15 16 17 18 19 20 21 22
RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT RB1 RB2 RB3
1 2 3 4 5 6 7 8 9 10 11
PIC16CR77 PIC16CR74
33 32 31 30 29 28 27 26 25 24 23
NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN VSS VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI
DS21993C-page 3
PIC16CR7X
Table of Contents
Device Overview ................................................................................................................................................................................... 5 Memory Organization .......................................................................................................................................................................... 13 Reading Program Memory .................................................................................................................................................................. 29 I/O Ports .............................................................................................................................................................................................. 31 Timer0 Module .................................................................................................................................................................................... 43 Timer1 Module .................................................................................................................................................................................... 47 Timer2 Module .................................................................................................................................................................................... 51 Capture/Compare/PWM Modules ....................................................................................................................................................... 53 Synchronous Serial Port (SSP) Module .............................................................................................................................................. 59 Universal Synchronous Asynchronous Receiver Transmitter (USART) ............................................................................................. 69 Analog-to-Digital Converter (A/D) Module ........................................................................................................................................... 83 Special Features of the CPU ............................................................................................................................................................... 89 Instruction Set Summary ................................................................................................................................................................... 105 Development Support ....................................................................................................................................................................... 113 Electrical Characteristics ................................................................................................................................................................... 117 DC and AC Characteristics Graphs and Tables ................................................................................................................................ 139 Packaging Information ...................................................................................................................................................................... 149 Appendix A: Revision History ........................................................................................................................................................... 159 Appendix B: Device Differences ........................................................................................................................................................ 159 Appendix C: Conversion Considerations .......................................................................................................................................... 160 The Microchip Web Site .................................................................................................................................................................... 167 Customer Change Notification Service ............................................................................................................................................. 167 Customer Support ............................................................................................................................................................................. 167 Reader Response ............................................................................................................................................................................. 168 Product Identification System ............................................................................................................................................................ 169
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DS21993C-page 4
(c) 2007 Microchip Technology Inc.
PIC16CR7X
1.0 DEVICE OVERVIEW
This document contains device specific information about the following devices: * * * * DSTEMP DSTEMP DSTEMP DSTEMP The available features are summarized in Table 1-1. Block diagrams of the PIC16CR73/76 and PIC16CR74/77 devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2 and Table 1-3. Additional information may be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
PIC16CR73/76 devices are available only in 28-pin packages, while PIC16CR74/77 devices are available in 40-pin and 44-pin packages. All devices in the PIC16CR7X family share common architecture, with the following differences: * The DSTEMP and DSTEMP have one-half of the total on-chip memory of the DSTEMP and DSTEMP * The 28-pin devices have 3 I/O ports, while the 40/44-pin devices have 5 * The 28-pin devices have 11 interrupts, while the 40/44-pin devices have 12 * The 28-pin devices have 5 A/D input channels, while the 40/44-pin devices have 8 * The Parallel Slave Port is implemented only on the 40/44-pin devices
TABLE 1-1:
PIC16CR7X DEVICE FEATURES
Key Features PIC16CR73 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 11 Ports A,B,C 3 2 SSP, USART -- 35 Instructions 28-pin DIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16CR74 DC - 20 MHz POR, BOR (PWRT, OST) 4K 192 12 Ports A,B,C,D,E 3 2 SSP, USART PSP 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP PIC16CR76 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 11 Ports A,B,C 3 2 SSP, USART -- 35 Instructions 28-pin DIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16CR77 DC - 20 MHz POR, BOR (PWRT, OST) 8K 368 12 Ports A,B,C,D,E 3 2 SSP, USART PSP 35 Instructions 40-pin PDIP 44-pin PLCC 44-pin TQFP
Operating Frequency Resets (and Delays) ROM Program Memory (14-bit words) Data Memory (bytes) Interrupts I/O Ports Timers Capture/Compare/PWM Modules Serial Communications Parallel Communications 8-bit Analog-to-Digital Module Instruction Set Packaging
5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
(c) 2007 Microchip Technology Inc.
DS21993C-page 5
PIC16CR7X
FIGURE 1-1: PIC16CR73 AND PIC16CR76 BLOCK DIAGRAM
13 Program Counter ROM Program Memory 8-Level Stack (13-bit) Program Bus 14 Instruction Reg Direct Addr 7
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB
RAM File Registers RAM Addr(1)
9
Addr MUX 8 Indirect Addr
FSR Reg STATUS Reg 8 PORTC Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8 W Reg 3 MUX
RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
ALU
MCLR
VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
CCP1
CCP2
Synchronous Serial Port
USART
Device PIC16CR73 PIC16CR76
Program ROM 4K 8K
Data Memory 192 Bytes 368 Bytes
Note
1:
Higher order bits are from the STATUS register.
DS21993C-page 6
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 1-2: PIC16CR74 AND PIC16CR77 BLOCK DIAGRAM
13 Program Counter ROM Program Memory 8-Level Stack (13-bit) Program Bus 14 Instruction Reg Direct Addr 7
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS PORTB RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTE RE0/AN5/RD RE1/AN6/WR RE2/AN7/CS
RAM File Registers RAM Addr(1)
9
Addr MUX 8 Indirect Addr
FSR Reg STATUS Reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
W Reg
MCLR
VDD, VSS
Timer0
Timer1
Timer2
8-bit A/D
CCP1
CCP2
Synchronous Serial Port
USART
Parallel Slave Port
Device
PIC16CR74 PIC16CR77
Program ROM
4K 8K
Data Memory
192 Bytes 368 Bytes
Note
1:
Higher order bits are from the STATUS register.
(c) 2007 Microchip Technology Inc.
DS21993C-page 7
PIC16CR7X
TABLE 1-2: PIC16CR73 AND PIC16CR76 PINOUT DESCRIPTION
PDIP SSOP SOIC Pin# 9 MLF Pin# 6 I I 10 7 O I/O/P Type Buffer Type
Pin Name
Description
OSC1/CLKIN OSC1 CLKIN OSC2/CLKOUT OSC2
ST/CMOS(3) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKIN, OSC2/CLKOUT pins). -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (Reset) input. This pin is an active low Reset to the device. PORTA is a bidirectional I/O port.
CLKOUT
O
MCLR
1
26
I
ST
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2 RA2 AN2 RA3/AN3/VREF RA3 AN3 VREF RA4/T0CKI RA4 T0CKI RA5/AN4/SS RA5 AN4 SS
2
27 I/O I
TTL Digital I/O. Analog input 0. TTL I/O I Digital I/O. Analog input 1. TTL I/O I Digital I/O. Analog input 2. TTL I/O I I Digital I/O. Analog input 3. A/D reference voltage input. ST I/O I Digital I/O - Open drain when configured as output. Timer0 external clock input. TTL I/O I I Digital I/O. Analog input 4. SPI slave select input. PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
3
28
4
1
5
2
6
3
7
4
RB0/INT RB0 INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 Legend: Note 1: 2: 3:
21
18 I/O I
TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL TTL TTL TTL TTL Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O.
22 23 24 25 26 27 28
19 20 21 22 23 24 25
I/O I/O I/O I/O I/O I/O I/O
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Verify mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS21993C-page 8
(c) 2007 Microchip Technology Inc.
PIC16CR7X
TABLE 1-2: PIC16CR73 AND PIC16CR76 PINOUT DESCRIPTION (CONTINUED)
PDIP SSOP SOIC Pin# 11 MLF Pin# I/O/P Type Buffer Type
Pin Name
Description
PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT VSS VDD Legend: Note 1: 2: 3: 8 I/O O I 12 9 I/O I I/O 13 10 I/O I/O 14 11 I/O I/O I/O 15 12 I/O I I/O 16 13 I/O O 17 14 I/O O I/O 18 15 I/O I I/O 8, 19 20 5, 16 17 P P -- -- ST Digital I/O. USART asynchronous receive. USART synchronous data. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. ST Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST Digital I/O. SPI data out. ST Digital I/O. SPI data in. I2CTM data I/O. ST Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST Digital I/O. Timer1 oscillator output. Timer1 external clock input.
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Verify mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
(c) 2007 Microchip Technology Inc.
DS21993C-page 9
PIC16CR7X
TABLE 1-3:
Pin Name OSC1/CLKIN OSC1 CLKIN
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION
PDIP Pin# 13 PLCC Pin# 14 QFP Pin# 30 I I I/O/P Type Buffer Type Description
ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKIN, OSC2/CLKOUT pins). -- Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Master Clear (Reset) input. This pin is an active low Reset to the device. PORTA is a bidirectional I/O port.
OSC2/CLKOUT OSC2
14
15
31 O
CLKOUT
O
MCLR
1
2
18
I
ST
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2 RA2 AN2 RA3/AN3/VREF RA3 AN3 VREF RA4/T0CKI RA4 T0CKI RA5/AN4/SS RA5 AN4 SS Legend: Note 1: 2: 3: 4:
2
3
19 I/O I
TTL Digital I/O. Analog input 0. TTL I/O I Digital I/O. Analog input 1. TTL I/O I Digital I/O. Analog input 2. TTL I/O I I Digital I/O. Analog input 3. A/D reference voltage input. ST I/O I Digital I/O - Open drain when configured as output. Timer0 external clock input. TTL I/O I I Digital I/O. Analog input 4. SPI slave select input.
3
4
20
4
5
21
5
6
22
6
7
23
7
8
24
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Verify mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS21993C-page 10
(c) 2007 Microchip Technology Inc.
PIC16CR7X
TABLE 1-3:
Pin Name
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION (CONTINUED)
PDIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
RB0/INT RB0 INT RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0/T1OSO/ T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: Note 1: 2: 3: 4:
33
36
8 I/O I
TTL/ST(1) Digital I/O. External interrupt. TTL TTL TTL TTL TTL TTL TTL ST I/O O I Digital I/O. Timer1 oscillator output. Timer1 external clock input. ST I/O I I/O Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O Digital I/O. Capture1 input/Compare1 output/PWM1 output. ST I/O I/O I/O Digital I/O. Synchronous serial clock input/output for SPI mode. Synchronous serial clock input/output for I2CTM mode. ST I/O I I/O Digital I/O. SPI data in. I2CTM data I/O. ST I/O O Digital I/O. SPI data out. ST I/O O I/O Digital I/O. USART asynchronous transmit. USART 1 synchronous clock. ST I/O I I/O Digital I/O. USART asynchronous receive. USART synchronous data. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. Digital I/O. PORTC is a bidirectional I/O port.
34 35 36 37 38 39 40 15
37 38 39 41 42 43 44 16
9 10 11 14 15 16 17 32
I/O I/O I/O I/O I/O I/O I/O
16
18
35
17
19
36
18
20
37
23
25
42
24
26
43
25
27
44
26
29
1
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Verify mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
(c) 2007 Microchip Technology Inc.
DS21993C-page 11
PIC16CR7X
TABLE 1-3:
Pin Name
PIC16CR74 AND PIC16CR77 PINOUT DESCRIPTION (CONTINUED)
PDIP Pin# PLCC Pin# QFP Pin# I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or parallel slave port when interfacing to a microprocessor bus.
RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 RE0/AN5/RD/ RE0 AN5 RD RE1/AN6/WR/ RE1 AN6 WR RE2/AN7/CS RE2 AN7 CS VSS VDD NC Legend: Note 1: 2: 3: 4:
19
21
38 I/O I/O
ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. ST/TTL(3) I/O I/O Digital I/O. Parallel Slave Port data. PORTE is a bidirectional I/O port. ST/TTL(3) I/O I I Digital I/O. Analog input 5. Read control for parallel slave port . ST/TTL(3) I/O I I Digital I/O. Analog input 6. Write control for parallel slave port . ST/TTL(3) I/O I I Digital I/O. Analog input 7. Chip Select control for parallel slave port . -- -- -- Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. These pins are not internally connected. These pins should be left unconnected.
20
22
39
I I/O I/O I I/O I/O
21
23
40
22
24
41
27
30
2
28
31
3
29
32
4
30
33
5
8
9
25
9
10
26
10
11
27
12,31 11,32 --
13,34 12,35 1,17, 28, 40
6,29 7,28 12,13, 33, 34
P P
I = input O = output I/O = input/output P = power -- = Not used TTL = TTL input ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as an external interrupt. This buffer is a Schmitt Trigger input when used in Serial Verify mode. This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
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PIC16CR7X
2.0 MEMORY ORGANIZATION
2.2 Data Memory Organization
There are two memory blocks in each of these PIC(R) MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can occur and is detailed in this section. The Program Memory can be read internally by user code (see Section 3.0 "Reading Program Memory"). Additional information on device memory may be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). The Data Memory is partitioned into multiple banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits: RP1:RP0 00 01 10 11 Bank 0 1 2 3
2.1
Program Memory Organization
The PIC16CR7X devices have a 13-bit program counter capable of addressing an 8K word x 14-bit program memory space. The PIC16CR77/76 devices have 8K words of ROM program memory and the PIC16CR73/74 devices have 4K words. The program memory maps for PIC16CR7X devices are shown in Figure 2-1. Accessing a location above the physically implemented address will cause a wraparound. The Reset vector is at 0000h and the interrupt vector is at 0004h.
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
The register file (shown in Figure 2-2 and Figure 2-3) can be accessed either directly, or indirectly, through the File Select Register (FSR).
FIGURE 2-1:
PROGRAM MEMORY MAPS AND STACKS FOR PIC16CR7X DEVICES
PIC16CR76/77
PC<12:0>
PIC16CR73/74
PC<12:0>
CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 2
13
CALL, RETURN RETFIE, RETLW Stack Level 1 Stack Level 2
13
Stack Level 8
Stack Level 8
Reset Vector Interrupt Vector Page 0
0000h 0004h 0005h On-Chip Program Memory
Reset Vector Interrupt Vector Page 0
0000h 0004h 0005h
07FFh 0800h On-Chip Program Memory Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh
07FFh 0800h Page 1 0FFFh 1000h
Unimplemented Read as `0'
1FFFh
(c) 2007 Microchip Technology Inc.
DS21993C-page 13
PIC16CR7X
FIGURE 2-2: PIC16CR77/76 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD(1) 88h TRISE(1) 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h SSPADD 93h SSPSTAT 94h 95h 96h 97h 98h TXSTA 99h SPBRG 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1 A0h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 Bank 1 File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch PMDATA PMADR 10Dh 10Eh PMDATH 10Fh PMADRH 110h 111h 112h 113h 114h 115h 116h General 117h Purpose 118h Register 119h 16 Bytes 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB File Address 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h
PCLATH INTCON PMCON1
General Purpose Register 16 Bytes
General Purpose Register 96 Bytes
EFh F0h FFh
General Purpose Register 80 Bytes accesses 70h-7Fh Bank 2
16Fh 170h 17Fh
General Purpose Register 80 Bytes accesses 70h-7Fh Bank 3
1EFh 1F0h 1FFh
Unimplemented data memory locations, read as `0'. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices.
DS21993C-page 14
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PIC16CR7X
FIGURE 2-3: PIC16CR74/73 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) 80h OPTION_REG 81h PCL 82h STATUS 83h FSR 84h TRISA 85h TRISB 86h TRISC 87h TRISD(1) 88h TRISE(1) 89h PCLATH 8Ah INTCON 8Bh PIE1 8Ch PIE2 8Dh PCON 8Eh 8Fh 90h 91h PR2 92h SSPADD 93h SSPSTAT 94h 95h 96h 97h 98h TXSTA 99h SPBRG 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh ADCON1 A0h General Purpose Register 96 Bytes File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch PMDATA PMADR 10Dh 10Eh PMDATH 10Fh PMADRH 110h File Address Indirect addr.(*) OPTION_REG PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON PMCON1
120h
1A0h
General Purpose Register 96 Bytes
accesses 20h-7Fh 16Fh 170h FFh 17Fh Bank 2
accesses A0h-FFh 1EFh 1F0h 1FFh Bank 3
7Fh Bank 0 Bank 1
Unimplemented data memory locations, read as `0'. * Not a physical register. Note 1: These registers are not implemented on 28-pin devices.
(c) 2007 Microchip Technology Inc.
DS21993C-page 15
PIC16CR7X
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address Bank 0 00h(4) 01h 02h(4) 03h(4) 04h(4) 05h 06h 07h 08h(5) 09h(5) 0Ah(1,4) 0Bh(4) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRES ADCON0 Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C(2)
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx --0x 0000 xxxx xxxx xxxx xxxx xxxx xxxx
27, 96 45, 96 26, 96 19, 96 27, 96 32, 96 34, 96 35, 96 36, 96 39, 96 26, 96 21, 96 23, 96 24, 96 50, 96 50, 96 47, 96 52, 96 52, 96 61, 96 56, 96 56, 96 54, 96 70, 96 75, 96 77, 96 58, 96 58, 96 54, 96 88, 96 83, 96
Indirect Data Memory Address Pointer -- -- PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read -- -- GIE PSPIF --
(3)
-- -- PEIE ADIF --
-- -- TMR0IE RCIF --
--
--
RE2
RE1
RE0
---- -xxx ---0 0000 0000 000x 0000 0000 ---- ---0 xxxx xxxx xxxx xxxx
Write Buffer for the upper 5 bits of the Program Counter INTE TXIF -- RBIE SSPIF -- TMR0IF CCP1IF -- INTF TMR2IF -- RBIF TMR1IF CCP2IF
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL -- T1CKPS1 T1CKPS0 TOUTPS1 CKP T1OSCEN T1SYNC TMR1CS Timer2 Module Register TOUTPS3 TOUTPS2 SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register SSPM3 SSPM2 SSPM1 SSPM0 Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 -- CCP1M2 FERR CCP1M1 OERR RX9D
TMR1ON --00 0000
0000 0000
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000
0000 0000 xxxx xxxx xxxx xxxx
xxxx xxxx 64, 68, 96
CCP1M0 --00 0000
0000 -00x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y CCP2M3 CCP2M2 GO/ DONE CCP2M1 A/D Result Register Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 -- ADON
CCP2M0 --00 0000
xxxx xxxx 0000 00-0
Legend: Note 1: 2: 3: 4: 5: 6:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter during branches (CALL or GOTO). Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
DS21993C-page 16
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PIC16CR7X
TABLE 2-1:
Address Bank 1 80h(4) 81h 82h(4) 83h(4) 84h(4) 85h 86h 87h 88h(5) 89h(5) 8Ah(1,4) 8Bh
(4)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page
Name
INDF OPTION_REG PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON -- -- -- PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- -- -- -- -- ADCON1
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 C(2)
0000 0000
27, 96
1111 1111 20, 44, 96 0000 0000 26, 96 19, 96 27, 96 32, 96 34, 96 35, 96 36, 96 38, 96 26, 96 21, 96 22, 97 24, 97 22, 97 -- -- -- 52, 97 68, 97 60, 97 -- -- -- 69, 97 71, 97
Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC
0001 1xxx xxxx xxxx --11 1111 1111 1111 1111 1111 1111 1111
Indirect data memory address pointer -- -- PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register IBF -- GIE PSPIE(3) -- -- OBF -- PEIE ADIE -- -- IBOV -- TMR0IE RCIE -- -- PSPMODE -- PORTE Data Direction Bits
0000 -111 ---0 0000 0000 000x 0000 0000 ---- ---0 ---- --qq -- -- -- 1111 1111 0000 0000
Write Buffer for the upper 5 bits of the Program Counter INTE TXIE -- -- RBIE SSPIE -- -- TMR0IF CCP1IE -- -- INTF TMR2IE -- POR RBIF TMR1IE CCP2IE BOR
8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh
Unimplemented Unimplemented Unimplemented Timer2 Module Period Register Synchronous Serial Port (I2CTM mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented -- -- -- -- -- PCFG2 PCFG1 PCFG0
0000 0000 -- -- -- 0000 -010 0000 0000 -- -- -- -- -- ---- -000
84, 97
Legend: Note 1: 2: 3: 4: 5: 6:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter during branches (CALL or GOTO). Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
(c) 2007 Microchip Technology Inc.
DS21993C-page 17
PIC16CR7X
TABLE 2-1:
Address Bank 2 100h(4) 101h 102h(4) 103h(4) 104h(4) 105h 106h 107h 108h 109h 10Bh(4) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(4) 181h 182h(4) 183h(4) 184h(4) 185h 186h 187h 188h 189h 18Bh(4) 18Ch 18Dh 18Eh 18Fh INDF OPTION_REG PCL STATUS FSR -- TRISB -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 27, 96
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page
Name
INDF TMR0 PCL STATUS FSR -- PORTB -- -- --
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx -- xxxx xxxx -- -- --
27, 96 45, 96 26, 96 19, 96 27, 96 -- 34, 96 -- -- -- 26, 96 21, 96 29, 97 29, 97 29, 97 29, 97
Indirect Data Memory Address Pointer Unimplemented PORTB Data Latch when written: PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INTE RBIE TMR0IF INTF RBIF
10Ah(1,4) PCLATH INTCON PMDATA PMADR PMDATH PMADRH
---0 0000 0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
Data Register Low Byte Address Register Low Byte -- -- -- -- Data Register High Byte -- Address Register High Byte
1111 1111 20, 44, 96 0000 0000 26, 96 19, 96 27, 96 -- 34, 96 -- -- -- 26, 96 21, 96 29, 97
Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx -- 1111 1111 -- -- --
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE --
(6)
18Ah(1,4) PCLATH INTCON PMCON1 -- -- --
-- PEIE --
-- TMR0IE --
Write Buffer for the upper 5 bits of the Program Counter INTE -- RBIE -- TMR0IF -- INTF -- RBIF RD
---0 0000 0000 000x 1--- ---0 -- 0000 0000 0000 0000
Unimplemented Reserved maintain clear Reserved maintain clear
Legend: Note 1: 2: 3: 4: 5: 6:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter during branches (CALL or GOTO). Other (non Power-up) Resets include external Reset through MCLR and Watchdog Timer Reset. Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear. These registers can be addressed from any bank. PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as `0'. This bit always reads as a `1'.
DS21993C-page 18
(c) 2007 Microchip Technology Inc.
PIC16CR7X
2.2.2.1 STATUS Register
The STATUS register contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable, therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any Status bits, see the "Instruction Set Summary." Note 1: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
R/W-0 IRP bit 7 Legend: R = Readable bit -n = Value at POR bit 7
STATUS: (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h-1FFh) 0 = Bank 0, 1 (00h-FFh) RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h-1FFh) 10 = Bank 2 (100h-17Fh) 01 = Bank 1 (80h-FFh) 00 = Bank 0 (00h-7Fh) Each bank is 128 bytes TO: Time-out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction
Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero
bit 6-5
bit 4
bit 3
bit 2
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 0
Note:
(c) 2007 Microchip Technology Inc.
DS21993C-page 19
PIC16CR7X
2.2.2.2 OPTION_REG Register
Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0 and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
REGISTER 2-2:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7
OPTION_REG: (ADDRESS 81h, 181h)
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual PORT latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
DS21993C-page 20
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PIC16CR7X
2.2.2.3 INTCON Register
Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-3:
R/W-0 GIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
INTCON: (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16CR7X
2.2.2.4 PIE1 Register
Note: The PIE1 register contains the individual enable bits for the peripheral interrupts. Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-4:
R/W-0 PSPIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7
(1)
PIE1: (ADDRESS 8Ch)
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt PSPIE is reserved on 28-pin devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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2.2.2.5 PIR1 Register
Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
REGISTER 2-5:
R/W-0 PSPIF(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7
PIR1: (ADDRESS 0Ch)
R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion is completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag 1 = The SSP interrupt condition has occurred, and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: SPI A transmission/reception has taken place. I2 C Slave A transmission/reception has taken place. I2 C Master A transmission/reception has taken place. The initiated Start condition was completed by the SSP module. The initiated Stop condition was completed by the SSP module. The initiated Restart condition was completed by the SSP module. The initiated Acknowledge condition was completed by the SSP module. A Start condition occurred while the SSP module was Idle (multi-master system). A Stop condition occurred while the SSP module was Idle (multi-master system). 0 = No SSP interrupt condition has occurred CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow PSPIF is reserved on 28-pin devices; always maintain this bit clear.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
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PIC16CR7X
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt.
REGISTER 2-6:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0
PIE2: (ADDRESS 8Dh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CCP2IE bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt
2.2.2.7
PIR2 Register
Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
The PIR2 register contains the flag bits for the CCP2 interrupt.
REGISTER 2-7:
U-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0
PIR2: (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 CCP2IF bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' CCP2IF: CCP2 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused
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2.2.2.8 PCON Register
Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. BOR is unknown on POR. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred. The BOR Status bit is not predictable if the brown-out circuit is disabled (by clearing the BOREN bit in the Configuration Word).
REGISTER 2-8:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1
PCON: (ADDRESS 8Eh)
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-1 BOR bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
bit 0
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PIC16CR7X
2.3 PCL and PCLATH
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-1 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
FIGURE 2-4:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
2.4
Program Memory Paging
PCH 12 PC 5
PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 Opcode <10:0> PCLATH 11 10 8 7 PCL 0 GOTO,CALL
PIC16CR7X devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH are unchanged after a RETURN or RETFIE instruction is executed. The user must setup the PCLATH for any subsequent CALLS or GOTOS.
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256 byte block). Refer to the Application Note, "Implementing a Table Read" (AN556).
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
EXAMPLE 2-1:
ORG BCF BSF
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
2.3.2
STACK
The PIC16CR7X family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed, or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.
0x500 PCLATH,4 PCLATH,3 ;Select page 1 ;(800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : ORG 0x900 ;page 1 (800h-FFFh) SUB1_P1 : : : RETURN ;called subroutine ;page 1 (800h-FFFh) ;return to Call ;subroutine in page 0 ;(000h-7FFh)
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PIC16CR7X
2.5 Indirect Addressing, INDF and FSR Registers
EXAMPLE 2-2:
MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register (FSR). Reading the INDF register itself indirectly (FSR = 0) will read 00h. Writing to the INDF register indirectly results in a no operation (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 2-2. A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
FIGURE 2-5:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR Register 0
RP1:RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0 Note 1:
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
For register file map detail, see Figure 2-2.
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PIC16CR7X
NOTES:
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PIC16CR7X
3.0 READING PROGRAM MEMORY
The ROM Program Memory is readable during normal operation over the entire VDD range. It is indirectly addressed through Special Function Registers (SFR). Up to 14-bit numbers can be stored in memory for use as calibration parameters, serial numbers, packed 7-bit ASCII, etc. Executing a program memory location containing data that forms an invalid instruction results in a NOP. There are five SFRs used to read the program and memory. These registers are: * * * * * PMCON1 PMDATA PMDATH PMADR PMADRH When interfacing to the program memory block, the PMDATH:PMDATA registers form a two-byte word, which holds the 14-bit data for reads. The PMADRH:PMADR registers form a two-byte word, which holds the 13-bit address of the ROM location being accessed. These devices can have up to 8K words of program ROM, with an address range from 0h to 3FFFh. The unused upper bits in both the PMDATH and PMADRH registers are not implemented and read as `0's.
3.1
PMADR
The address registers can address up to a maximum of 8K words of program ROM. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADR register. The upper MSb's of PMADRH must always be clear.
The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration tables.
3.2
PMCON1 Register
PMCON1 is the control register for memory accesses. The control bit RD initiates read operations. This bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the read operation.
REGISTER 3-1:
R-1 reserved bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-1 bit 0
PMCON1: (ADDRESS 18Ch)
U-0 -- U-0 -- U-0 -- U-x -- U-0 -- U-0 -- R/S-0 RD bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Reserved: Read as `1' Unimplemented: Read as `0' RD: Read Control bit 1 = Initiates a ROM read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = ROM read completed
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PIC16CR7X
3.3 Reading the ROM Program Memory 3.4 Operation During Code-Protect
ROM program memory has its own code-protect mechanism. External Read operations by programmers are disabled if this mechanism is enabled. The microcontroller can read and execute instructions out of the internal ROM program memory, regardless of the state of the code-protect Configuration bits.
A program memory location may be read by writing two bytes of the address to the PMADR and PMADRH registers and then setting control bit RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycles to read the data. The data is available in the PMDATA and PMDATH registers after the second NOP instruction. Therefore, it can be read as two bytes in the following instructions. The PMDATA and PMDATH registers will hold this value until the next read operation.
EXAMPLE 3-1:
BSF BCF MOVF MOVWF MOVF MOVWF BSF Required Sequence BSF NOP NOP BCF MOVF MOVF
ROM PROGRAM READ
STATUS, RP1 STATUS, RP0 ADDRH, W PMADRH ADDRL, W PMADR STATUS, RP0 PMCON1, RD ; ; ; ; ; ; ; Bank 2 MSByte of Program Address to read LSByte of Program Address to read Bank 3 Required
; ROM Read Sequence ; memory is read in the next two cycles after BSF PMCON1,RD ; ; Bank 2 ; W = LSByte of Program PMDATA ; W = MSByte of Program PMDATA
STATUS, RP0 PMDATA, W PMDATH, W
TABLE 3-1:
Address 10Dh 10Fh 10Ch 10Eh 18Ch Legend: Note 1: Name
REGISTERS ASSOCIATED WITH PROGRAM ROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
PMADR PMADRH
Address Register Low Byte -- -- -- Address Register High Byte
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu -- -- RD 1--- ---0 1--- ---0
PMDATA Data Register Low Byte PMDATH PMCON1 -- --(1) -- -- Data Register High Byte -- -- --
x = unknown, u = unchanged, r = reserved, - = unimplemented read as `0'. Shaded cells are not used during ROM access. This bit always reads as a `1'.
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PIC16CR7X
4.0 I/O PORTS
FIGURE 4-1:
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS
Q VDD Q
Data Bus
D
WR Port
CK
P
Data Latch N I/O pin(1)
4.1
PORTA and the TRISA Register
WR TRIS
D
Q Q Analog Input Mode VSS
PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impendance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the PORT data latch. Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other PORTA pins have TTL input levels and full CMOS output drivers. Other PORTA pins are multiplexed with analog inputs and analog VREF input. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). Note: On a Power-on Reset, these pins are configured as analog inputs and read as `0'.
CK
TRIS Latch
RD TRIS Q D EN EN
TTL Input Buffer
RD PORT
To A/D Converter Note 1: I/O pins have protection diodes to VDD and VSS.
FIGURE 4-2:
BLOCK DIAGRAM OF RA4/T0CKI PIN
D Q Q N VSS Schmitt Trigger Input Buffer
Data Bus WR PORT
CK
I/O pin(1)
The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set, when using them as analog inputs.
Data Latch D WR TRIS Q Q
CK
TRIS Latch
EXAMPLE 4-1:
BCF BCF CLRF
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Bank0 Initialize PORTA by clearing output data latches Select Bank 1 Configure all pins as digital inputs Value used to initialize data direction Set RA<3:0> as inputs RA<5:4> as outputs TRISA<7:6>are always read as `0'.
RD TRIS Q
STATUS, RP0 STATUS, RP1 PORTA
D EN EN
BSF MOVLW MOVWF MOVLW
STATUS, RP0 0x06 ADCON1 0xCF
RD PORT
TMR0 Clock Input Note 1: I/O pin has protection diodes to VSS only.
MOVWF
TRISA
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TABLE 4-1:
Name RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/VREF RA4/T0CKI RA5/AN4/SS
PORTA FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 Buffer TTL TTL TTL TTL ST TTL Input/output or analog input. Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF. Input/output or external clock input for Timer0. Output is open drain type. Input/output or slave select input for synchronous serial port or analog input. Function
Legend: TTL = TTL input, ST = Schmitt Trigger input
TABLE 4-2:
Address 05h 85h 9Fh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 RA5 -- Bit 4 RA4 -- Bit 3 RA3 -- Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR
--0x 0000 --11 1111
Value on all other Resets
--0u 0000 --11 1111 ---- -000
PORTA TRISA ADCON1
PORTA Data Direction Register
PCFG2 PCFG1 PCFG0 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA.
Note:
When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of the following modes where PCFG2:PCFG0 = 100, 101, 11x.
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4.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impendance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. This interrupt can wake the device from Sleep. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. This interrupt on mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, "Implementing Wake-up on Key Stroke" (AN552). RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION_REG<6>). RB0/INT is discussed in detail in Section 12.11.1 "INT Interrupt".
FIGURE 4-3:
BLOCK DIAGRAM OF RB3:RB0 PINS
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(1)
RBPU(2)
Data Bus WR Port
WR TRIS
CK
TTL Input Buffer
FIGURE 4-4:
BLOCK DIAGRAM OF RB7:RB4 PINS
VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(1)
RD TRIS Q RD Port EN D
RBPU(2)
Data Bus WR Port
RB0/INT Schmitt Trigger Buffer RD Port WR TRIS
CK
Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). RD TRIS Latch Q RD Port
TTL Input Buffer
Four of the PORTB pins (RB7:RB4) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are ORed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
D EN Q1
Set RBIF
Q From other RB7:RB4 pins
D RD Port EN Q3
Note
1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
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PIC16CR7X
TABLE 4-3:
Name RB0/INT RB1 RB2 RB3 RB4 RB5 RB6 RB7
PORTB FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer TTL/ST(1) TTL TTL TTL TTL TTL TTL TTL Function Input/output pin or external interrupt input. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
TABLE 4-4:
Address 06h, 106h 86h, 186h 81h, 181h Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU Bit 6 RB6 INTEDG Bit 5 RB5 T0CS Bit 4 RB4 T0SE Bit 3 RB3 PSA Bit 2 RB2 PS2 Bit 1 RB1 PS1 Bit 0 RB0 PS0 Value on POR, BOR Value on all other Resets
PORTB TRISB OPTION_REG
xxxx xxxx uuuu uuuu 1111 1111 1111 1111 1111 1111 1111 1111
PORTB Data Direction Register
x = unknown, u = unchanged. Shaded cells are not used by PORTB.
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4.3 PORTC and the TRISC Register
FIGURE 4-5:
PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impendance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 4-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings, and to Section 13.1 "READ-MODIFY-WRITE OPERATIONS" for additional information on read-modify-write operations.
WR TRIS
PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE)
Port/Peripheral Select(2) Peripheral Data Out Data Bus WR Port 0 D CK Q 1 Q Data Latch D CK Q Q N VSS RD TRIS Peripheral OE(3) Q D EN RD Port Peripheral Input Note 1: 2: 3: I/O pins have diode protection to VDD and VSS. Port/Peripheral select signal selects between PORT data and peripheral output. Peripheral OE (output enable) is only activated if peripheral select is active. Schmitt Trigger I/O pin(1) VDD P
TRIS Latch
TABLE 4-5:
Name
PORTC FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output/Timer1 clock input. Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. Input/output port pin or Capture1 input/Compare1 output/PWM1 output. RC3 can also be the synchronous serial clock for both SPI and I2CTM modes. RC4 can also be the SPI Data In (SPI mode) or Data I/O (I2CTM mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin or USART Asynchronous Transmit or Synchronous Clock. Input/output port pin or USART Asynchronous Receive or Synchronous Data.
RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT
Legend: ST = Schmitt Trigger input
TABLE 4-6:
Address 07h 87h
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Bit 7 RC7 Bit 6 RC6 Bit 5 RC5 Bit 4 RC4 Bit 3 RC3 Bit 2 RC2 Bit 1 RC1 Bit 0 RC0 Value on POR, BOR Value on all other Resets
Name PORTC TRISC
xxxx xxxx uuuu uuuu 1111 1111 1111 1111
PORTC Data Direction Register
Legend: x = unknown, u = unchanged
(c) 2007 Microchip Technology Inc.
DS21993C-page 35
PIC16CR7X
4.4 PORTD and TRISD Registers
FIGURE 4-6:
This section is not applicable to the PIC16CR73 or PIC16CR76. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configureable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PORTD BLOCK DIAGRAM (IN I/O PORT MODE)
D Q I/O pin(1) CK Data Latch D Q Schmitt Trigger Input Buffer
Data Bus WR Port
WR TRIS
CK TRIS Latch
RD TRIS Q D EN EN RD Port
Note 1: I/O pins have protection diodes to VDD and VSS.
TABLE 4-7:
Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7
PORTD FUNCTIONS
Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL
(1)
Function Input/output port pin or parallel slave port bit 0 Input/output port pin or parallel slave port bit 1 Input/output port pin or parallel slave port bit 2 Input/output port pin or parallel slave port bit 3 Input/output port pin or parallel slave port bit 4 Input/output port pin or parallel slave port bit 5 Input/output port pin or parallel slave port bit 6 Input/output port pin or parallel slave port bit
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-8:
Address 08h 88h 89h Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Bit 7 RD7 IBF Bit 6 RD6 OBF Bit 5 RD5 IBOV Bit 4 RD4 PSPMODE Bit 3 RD3 -- Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 Value on POR, BOR xxxx xxxx 1111 1111 PORTE Data Direction bits 0000 -111 Value on all other Resets uuuu uuuu 1111 1111 0000 -111
Name PORTD TRISD TRISE
PORTD Data Direction Register
x = unknown, u = unchanged, - = unimplemented read as `0'. Shaded cells are not used by PORTD.
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PIC16CR7X
4.5 PORTE and TRISE Register
FIGURE 4-7:
This section is not applicable to the PIC16CR73 or PIC16CR76. PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7, which are individually configureable as inputs or outputs. These pins have Schmitt Trigger input buffers. I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). Ensure ADCON1 is configured for digital I/O. In this mode, the input buffers are TTL. Register 4-1 shows the TRISE register, which also controls the Parallel Slave Port operation. PORTE pins are multiplexed with analog inputs. When selected as an analog input, these pins will read as `0's. TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a Power-on Reset, these pins are configured as analog inputs and read as `0'.
RD Port Note 1: I/O pins have protection diodes to VDD and VSS.
PORTE BLOCK DIAGRAM (IN I/O PORT MODE)
D Q I/O pin(1) CK Data Latch D Q Schmitt Trigger Input Buffer
Data Bus WR Port
WR TRIS
CK TRIS Latch
RD TRIS Q D EN EN
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
REGISTER 4-1:
R-0 IBF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
TRISE: (ADDRESS 89h)
R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- R/W-1 Bit 2 R/W-1 Bit 1 R/W-1 Bit 0 bit 0
Parallel Slave Port Status/Control bits: IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General Purpose I/O mode Unimplemented: Read as `0' PORTE Data Direction bits: Bit 2: Direction Control bit for pin RE2/CS/AN7 1 = Input 0 = Output Bit 1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output Bit 0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
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PIC16CR7X
TABLE 4-9:
Name RE0/RD/AN5
PORTE FUNCTIONS
Bit# bit 0 Buffer Type ST/TTL(1) Function Input/output port pin or read control input in Parallel Slave Port mode or analog input. For RD (PSP mode): 1 = Idle 0 = Read operation. Contents of PORTD register output to PORTD I/O pins (if chip selected). Input/output port pin or write control input in Parallel Slave Port mode or analog input. For WR (PSP mode): 1 = Idle 0 = Write operation. Value of PORTD I/O pins latched into PORTD register (if chip selected). Input/output port pin or Chip Select control input in Parallel Slave Port mode or analog input. For CS (PSP mode): 1 = Device is not selected 0 = Device is selected
RE1/WR/AN6
bit 1
ST/TTL(1)
RE2/CS/AN7
bit 2
ST/TTL(1)
Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.
TABLE 4-10:
Addr 09h 89h 9Fh Name PORTE TRISE ADCON1
SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Bit 7 -- IBF -- Bit 6 -- OBF -- Bit 5 -- IBOV -- Bit 4 -- PSPMODE -- Bit 3 -- -- -- Bit 2 RE2 PCFG2 Bit 1 RE1 PCFG1 Bit 0 RE0 PCFG0 Value on POR, BOR ---- -xxx 0000 -111 ---- -000 Value on all other Resets ---- -uuu 0000 -111 ---- -000
PORTE Data Direction bits
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PORTE.
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
4.6 Parallel Slave Port
The Parallel Slave Port (PSP) is not implemented on the PIC16CR73 or PIC16CR76. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by an external system using the read control input pin RE0/RD, the write control input pin RE1/WR, and the Chip Select control input pin RE2/ CS. The PSP can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (Chip Select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (i.e., set). The A/D port Configuration bits PCFG3:PCFG0 (ADCON1<3:0>) must be set to configure pins RE2:RE0 as digital I/O. There are actually two 8-bit latches, one for data output (external reads) and one for data input (external writes). The firmware writes 8-bit data to the PORTD output data latch and reads data from the PORTD input data latch (note that they have the same address). In this mode, the TRISD register is ignored, since the external device is controlling the direction of data flow. An external write to the PSP occurs when the CS and WR lines are both detected low. Firmware can read the actual data on the PORTD pins during this time. When either the CS or WR lines become high (level triggered), the data on the PORTD pins is latched, and the Input Buffer Full (IBF) status flag bit (TRISE<7>) and interrupt flag bit PSPIF (PIR1<7>) are set on the Q4 clock cycle, following the next Q2 cycle to signal the write is complete (Figure 4-9). Firmware clears the IBF flag by reading the latched PORTD data and clears the PSPIF bit. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if an external write to the PSP occurs while the IBF flag is set from a previous external write. The previous PORTD data is overwritten with the new data. IBOV is cleared by reading PORTD and clearing IBOV. A read from the PSP occurs when both the CS and RD lines are detected low. The data in the PORTD output latch is output to the PORTD pins. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 4-10), indicating that the PORTD latch is being read, or has been read by the external bus. If firmware writes new data to the output latch during this time, it is immediately output to the PORTD pins, but OBF will remain cleared. When either the CS or RD pins are detected high, the PORTD outputs are disabled, and the interrupt flag bit PSPIF is set on the Q4 clock cycle following the next Q2 cycle, indicating that the read is complete. OBF remains low until firmware writes new data to PORTD. When not in PSP mode, the IBF and OBF bits are held clear. Flag bit IBOV remains unchanged. The PSPIF bit must be cleared by the user in firmware; the interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).
FIGURE 4-8:
PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT)
Data Bus D WR Port Q RDx pin TTL Q RD Port One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) D EN EN
CK
Read
TTL
RD
Chip Select TTL Write TTL Note: I/O pin has protection diodes to VDD and VSS.
CS
WR
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PIC16CR7X
FIGURE 4-9: PARALLEL SLAVE PORT WRITE WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
FIGURE 4-10:
PARALLEL SLAVE PORT READ WAVEFORMS
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CS WR RD PORTD<7:0> IBF OBF PSPIF
TABLE 4-11:
Address 08h 09h 89h 0Ch 8Ch 9Fh Legend: Note 1:
REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx RE1 RE0 ---- -xxx 0000 -111 0000 0000 0000 0000 ---- -000 Value on all other Resets uuuu uuuu ---- -uuu 0000 -111 0000 0000 0000 0000 ---- -000
Name PORTD PORTE TRISE PIR1 PIE1 ADCON1
PORT data latch when written: Port pins when read -- IBF PSPIF(1) -- OBF ADIF -- RCIF RCIE -- -- TXIF TXIE -- -- -- SSPIF SSPIE -- RE2 IBOV PSPMODE PORTE Data Direction Bits CCP1IF TMR2IF TMR1IF CCP1IE TMR2IE TMR1IE PCFG2 PCFG1 PCFG0
PSPIE(1) ADIE -- --
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Parallel Slave Port. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
(c) 2007 Microchip Technology Inc.
DS21993C-page 41
PIC16CR7X
NOTES:
DS21993C-page 42
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PIC16CR7X
5.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2 "Using Timer0 with an External Clock". The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 5.3 "Prescaler" details the operation of the prescaler.
Additional information on the Timer0 module is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). Figure 5-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT. Timer0 operation is controlled through the OPTION_REG register (Register 5-1 on the following page). Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.
5.1
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from Sleep, since the timer is shut-off during Sleep.
FIGURE 5-1:
CLKOUT (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0 MODULE AND PRESCALER
Data Bus 8 1 0 M U X SYNC 2 Cycles TMR0 Reg
0 RA4/T0CKI pin 1 T0SE
M U X
T0CS
PSA PRESCALER
Set Flag bit TMR0IF on Overflow
0 M U X
8-bit Prescaler 8 8-to-1 MUX PS2:PS0
Watchdog Timer
1
PSA 0 MUX 1 PSA
WDT Enable bit
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
5.2 Using Timer0 with an External Clock
Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
REGISTER 5-1:
R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5
OPTION_REG:
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RBPU: PORTB Pull-up Enable bit (see Section 2.2.2.2 "OPTION_REG Register") INTEDG: Interrupt Edge Select bit (see Section 2.2.2.2 "OPTION_REG Register") T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS2:PS0: Prescaler Rate Select bits
Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 WDT Rate 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 4
bit 3
bit 2-0
Note:
To avoid an unintended device Reset, the instruction sequences shown in Example 5-1 and Example 5-2 must be executed when changing the prescaler assignment between Timer0 and the WDT. This sequence must be followed even if the WDT is disabled.
DS21993C-page 44
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PIC16CR7X
5.3 Prescaler
There is only one prescaler available on the microcontroller; it is shared exclusively between the Timer0 module and the Watchdog Timer. The usage of the prescaler is also mutually exclusive: that is, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice versa. This prescaler is not readable or writable (see Figure 5-1). The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Examples of code for assigning the prescaler assignment are shown in Example 5-1 and Example 5-2. Note that when the prescaler is being assigned to the WDT with ratios other than 1:1, lines 2 and 3 (highlighted) are optional. If a prescale ratio of 1:1 is used, however, these lines must be used to set a temporary value. The final 1:1 value is then set in lines 10 and 11 (highlighted). (Line numbers are included in the example for illustrative purposes only, and are not part of the actual code.) When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.
EXAMPLE 5-1:
1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) BSF MOVLW MOVWF BCF CLRF BSF MOVLW MOVWF CLRWDT MOVLW MOVWF BCF
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
; ; ; ; ; ; ; Bank1 Select clock source and prescale value of other than 1:1 Bank0 Clear TMR0 and prescaler Bank1 Select WDT, do not change prescale value
STATUS, RP0 b'xx0x0xxx' OPTION_REG STATUS, RP0 TMR0 STATUS, RP1 b'xxxx1xxx' OPTION_REG b'xxxx1xxx' OPTION_REG STATUS, RP0
; Clears WDT and prescaler ; Select new prescale value and WDT ; Bank0
EXAMPLE 5-2:
CLRWDT BSF MOVLW MOVWF BCF
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
; ; ; ; ; Clear WDT and prescaler Bank1 Select TMR0, new prescale value and clock source Bank0
STATUS, RP0 b'xxxx0xxx' OPTION_REG STATUS, RP0
TABLE 5-1:
Address 01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE RBIE PSA TMR0IF PS2 INTF PS1 RBIF PS0 0000 000x 1111 1111 Value on all other Resets uuuu uuuu 0000 000u 1111 1111
TMR0
Timer0 Module Register GIE PEIE TMR0IE T0CS
0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h Legend:
OPTION_REG RBPU INTEDG
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0.
(c) 2007 Microchip Technology Inc.
DS21993C-page 45
PIC16CR7X
NOTES:
DS21993C-page 46
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PIC16CR7X
6.0 TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>). Timer1 can operate in one of two modes: * As a timer * As a counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). Timer1 also has an internal "Reset input". This Reset can be generated by either of the two CCP modules as the special event trigger (see Sections 8.1 and 8.2). Register 6-1 shows the Timer1 Control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as `0'. Additional information on timer modules is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
REGISTER 6-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4
T1CON: TIMER1 CONTROL (ADDRESS 10h)
U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
Unimplemented: Read as `0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1
bit 3
bit 2
bit 1
bit 0
(c) 2007 Microchip Technology Inc.
DS21993C-page 47
PIC16CR7X
6.1 Timer1 Operation in Timer Mode 6.2 Timer1 Counter Operation
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.
FIGURE 6-1:
T1CKI (Default high)
TIMER1 INCREMENTING EDGE
T1CKI (Default low)
Note: Arrows indicate counter increments.
6.3
Timer1 Operation in Synchronized Counter Mode
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RC1/T1OSI/CCP2, when bit T1OSCEN is set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN is cleared.
If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration, during Sleep mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.
FIGURE 6-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0
Synchronized Clock Input
1 TMR1ON On/Off T1OSC RC0/T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock
(2)
T1SYNC Prescaler 1, 2, 4, 8 Synchronize det Q Clock
1
RC1/T1OSI/CCP2(2)
0 2 T1CKPS1:T1CKPS0 TMR1CS
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain. 2: For the PIC16CR73/76, the Schmitt Trigger is not implemented in External Clock mode.
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PIC16CR7X
6.4 Timer1 Operation in Asynchronous Counter Mode
6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 6.4.1 "Reading and writing Timer1 in asynchronous counter mode"). In Asynchronous Counter mode, Timer1 cannot be used as a time base for capture or compare operations.
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. The example code provided in Example 6-1 and Example 6-2 demonstrates how to write to and read Timer1 while it is running in Asynchronous mode.
EXAMPLE 6-1:
WRITING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled CLRF TMR1L ; Clear Low byte, Ensures no rollover into TMR1H MOVLW HI_BYTE ; Value to load into TMR1H MOVWF TMR1H, F ; Write High byte MOVLW LO_BYTE ; Value to load into TMR1L MOVWF TMR1H, F ; Write Low byte ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
EXAMPLE 6-2:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL MOVF TMR1H, W ; Read high byte SUBWF TMPH, W ; Sub 1st read with 2nd read BTFSC STATUS,Z ; Is result = 0 GOTO CONTINUE ; Good 16-bit read ; TMR1L may have rolled over between the read of the high and low bytes. ; Reading the high and low bytes now will read a good value. MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
6.5 Timer1 Oscillator
TABLE 6-1:
A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 200 kHz. It will continue to run during Sleep. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator. The Timer1 oscillator is identical to the LP oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Capacitors Used: Frequency OSC1 OSC2
Osc Type LP
32 kHz 47 pF 47 pF 100 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes (below) table for additional information. Commonly Used Crystals: 32.768 kHz Epson C-001R32.768K-A 100 kHz Epson C-2 100.00 KC-P 200 kHz STD XTL 200.000 kHz Note 1: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected.
6.6
Resetting Timer1 using a CCP Trigger Output
If the CCP1 or CCP2 module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1. Note: The special event triggers from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchronized Counter mode, to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence. In this mode of operation, the CCPRxH:CCPRxL register pair effectively becomes the period register for Timer1.
6.7
Resetting of Timer1 Register Pair (TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers.
6.8
Timer1 Prescaler
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
TABLE 6-2:
Address Name
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR1ON --00 0000 Value on all other Resets 0000 000u 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --uu uuuu
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: Note 1: PIR1 PIE1 TMR1L TMR1H T1CON
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
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PIC16CR7X
7.0 TIMER2 MODULE
7.1 Timer2 Prescaler and Postscaler
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon Reset. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Register 7-1 shows the Timer2 control register. Additional information on timer modules is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
Postscaler 1:1 to 1:16 4 T2OUTPS3: T2OUTPS0 Note 1: TMR2 register output can be software selected by the SSP module as a baud clock. EQ
The prescaler and postscaler counters are cleared when any of the following occurs: * a write to the TMR2 register * a write to the T2CON register * any device Reset (POR, MCLR Reset, WDT Reset or BOR) TMR2 is not cleared when T2CON is written.
7.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate shift clock.
FIGURE 7-1:
Sets Flag bit TMR2IF TMR2 Output(1) Reset
TIMER2 BLOCK DIAGRAM
TMR2 Reg Comparator
Prescaler 1:1, 1:4, 1:16 2 T2CKPS1: T2CKPS0
FOSC/4
PR2 Reg
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PIC16CR7X
REGISTER 7-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
T2CON: TIMER2 CONTROL (ADDRESS 12h)
R/W-0 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0
TOUTPS3
Unimplemented: Read as `0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16
bit 2
bit 1-0
TABLE 7-1:
Address Name
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 1111 1111 Value on all other Resets 0000 000u 0000 0000 0000 0000 0000 0000 -000 0000 1111 1111
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 8Ch 11h 12h 92h Legend: Note 1: PIR1 PIE1 TMR2 T2CON PR2
GIE PSPIF(1) PSPIE
(1)
PEIE ADIF ADIE
TMR0IE RCIF RCIE
INTE TXIF TXIE
RBIE SSPIF SSPIE
TMR0IF CCP1IF CCP1IE
INTF TMR2IF TMR2IE
RBIF TMR1IF TMR1IE
Timer2 Module Register -- TOUTPS3
Timer2 Period Register
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
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PIC16CR7X
8.0 CAPTURE/COMPARE/PWM MODULES
8.2 CCP2 Module
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match; it will clear both TMR1H and TMR1L registers, and start an A/D conversion (if the A/D module is enabled). Additional information on CCP modules is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023) and in Application Note AN594, "Using the CCP Modules" (DS00594).
Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted.
TABLE 8-1:
CCP MODE - TIMER RESOURCES REQUIRED
Timer Resource Timer1 Timer1 Timer2
8.1
CCP1 Module
CCP Mode Capture Compare PWM
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will clear both TMR1H and TMR1L registers.
TABLE 8-2:
Capture Capture Compare PWM PWM PWM
INTERACTION OF TWO CCP MODULES
Interaction Same TMR1 time base. Same TMR1 time base. Same TMR1 time base. The PWMs will have the same frequency and update rate (TMR2 interrupt). The rising edges are aligned. None. None. Capture Compare Compare PWM Capture Compare
CCPx Mode CCPy Mode
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
REGISTER 8-1:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CCP1CON/CCP2CON: (ADDRESS 17h/1Dh)
U-0 -- R/W-0 CCPxX R/W-0 CCPxY R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0
Unimplemented: Read as `0' CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set, CCPx pin is unaffected); CCP1 clears Timer1; CCP2 clears Timer1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode
bit 3-0
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PIC16CR7X
8.3 Capture Mode
8.3.4 CCP PRESCALER
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following and is configured by CCPxCON<3:0>: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
EXAMPLE 8-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
8.3.1
CCP PIN CONFIGURATION
MOVWF
In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 pin is configured as an output, a write to the port can cause a capture condition.
CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCP1CON ;Load CCP1CON with this ;value
8.4
Compare Mode
FIGURE 8-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.
Set Flag bit CCP1IF (PIR1<2>) Prescaler / 1, 4, 16 RC2/CCP1 pin and Edge Detect CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's TMR1L CCPR1L
FIGURE 8-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCP1CON<3:0> Mode Select Set Flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S R Output Logic Comparator TMR1H TMR1L
8.3.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
8.3.3
SOFTWARE INTERRUPT
RC2/CCP1 Pin TRISC<2> Output Enable
Match
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.
Special Event Trigger Special Event Trigger will: * clear TMR1H and TMR1L registers * NOT set interrupt flag bit TMR1F (PIR1<0>) * (for CCP2 only) set the GO/DONE bit (ADCON0<2>)
(c) 2007 Microchip Technology Inc.
DS21993C-page 55
PIC16CR7X
8.4.1 CCP PIN CONFIGURATION 8.4.4 SPECIAL EVENT TRIGGER
The user must configure the RC2/CCP1 pin as an output by clearing the TRISC<2> bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the PORTC I/O data latch. In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special event trigger output of CCP2 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The special event trigger from the CCP1 and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).
8.4.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
8.4.3
SOFTWARE INTERRUPT MODE
When Generate Software Interrupt mode is chosen, the CCP1 pin is not affected. The CCP1IF or CCP2IF bit is set, causing a CCP interrupt (if enabled).
TABLE 8-3:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Bit 7 GIE PSPIF(1) -- PSPIE(1) -- Bit 6 PEIE ADIF -- ADIE -- Bit 5 TMR0IE RCIF -- RCIE -- Bit 4 INTE TXIF -- TXIE -- Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF -- CCP1IE -- Bit 1 INTF TMR2IF -- Bit 0 RBIF Value on POR, BOR Value on all other Resets
Name
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 0Dh 8Ch 8Dh 87h 0Eh 0Fh 10h 15h 16h 17h 1Bh 1Ch 1Dh Legend: Note 1: PIR1 PIR2 PIE1 PIE2 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0
TMR2IE TMR1IE 0000 0000 0000 0000 -- CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
PORTC Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- --
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- CCP1X CCP1Y
Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1. The PSP is not implemented on the PIC16CR73/76; always maintain these bits clear.
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PIC16CR7X
8.5 PWM Mode (PWM)
8.5.1 PWM PERIOD
In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 8.3 "Capture Mode") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 8.5.3 "SetUp for PWM Operation".
FIGURE 8-3:
Duty Cycle Registers CCPR1L
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
8.5.2
CCPR1H (Slave) R Q RC2/CCP1 TMR2 (Note 1) Comparator Clear Timer, CCP1 pin and latch D.C. (1) S TRISC<2>
PWM DUTY CYCLE
Comparator
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the formula: FOSC log( FPWM Resolution = bits log(2)
PR2
Note 1: The 8-bit timer is concatenated with the 2-bit internal Q clock or the 2 bits of the prescaler to create the 10-bit time base.
A PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 8-4:
TMR2 Reset Period
PWM OUTPUT
TMR2 Reset
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
)
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
(c) 2007 Microchip Technology Inc.
DS21993C-page 57
PIC16CR7X
8.5.3 SETUP FOR PWM OPERATION
3. 4. 5. The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
TABLE 8-4:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz)
1.22 kHz 16 0xFF 10 4.88 kHz 4 0xFF 10 19.53 kHz 1 0xFF 10 78.12 kHz 1 0x3F 8 156.3 kHz 1 0x1F 7 208.3 kHz 1 0x17 5.5
PWM Frequency Timer Prescale (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 8-5:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE PSPIF(1) -- PSPIE --
(1)
Name
Bit 6 PEIE ADIF -- ADIE --
Bit 5 TMR0IE RCIF -- RCIE --
Bit 4 INTE TXIF -- TXIE --
Bit 3 RBIE SSPIF -- SSPIE --
Bit 2 TMR0IF CCP1IF --
Bit 1 INTF TMR2IF --
Bit 0 RBIF
Value on POR, BOR
Value on all other Resets
0Bh,8Bh, INTCON 10Bh,18Bh 0Ch 0Dh 8Ch 8Dh 87h 11h 92h 12h 15h 16h 17h 1Bh 1Ch 1Dh Legend: Note 1: PIR1 PIR2 PIE1 PIE2 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON
0000 000x 0000 000u
TMR1IF 0000 0000 0000 0000 CCP2IF ---- ---0 ---- ---0 TMR1IE 0000 0000 0000 0000 CCP2IE ---- ---0 ---- ---0 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
CCP1IE TMR2IE -- --
PORTC Data Direction Register Timer2 Module Register Timer2 Module Period Register --
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- CCP1X CCP1Y
Capture/Compare/PWM Register 2 (LSB) Capture/Compare/PWM Register 2 (MSB) -- -- CCP2X CCP2Y
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
DS21993C-page 58
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PIC16CR7X
9.0
9.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
9.2
SPI Mode
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) An overview of I2C operations and additional information on the SSP module can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). Refer to Application Note AN578, "Use of the SSP Module in the I 2CTM Multi-Master Environment" (DS00578).
This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) RC5/SDO * Serial Data In (SDI) RC4/SDI/SDA * Serial Clock (SCK) RC3/SCK/SCL Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) RA5/SS/AN4 When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified: * * * * Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Clock edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only)
(c) 2007 Microchip Technology Inc.
DS21993C-page 59
PIC16CR7X
REGISTER 9-1:
R/W-0 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPSTAT: SYNC SERIAL PORT STATUS (ADDRESS 94h)
R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0
SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire) SPI Slave mode: SMP must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear CKE: SPI Clock Edge Select bit (Figure 9-2, Figure 9-3, and Figure 9-4) SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK (Microwire alternate) 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK (Microwire default) 0 = Data transmitted on rising edge of SCK I2 C mode: This bit must be maintained clear D/A: Data/Address bit (I2CTM mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: Stop bit (I2CTM mode only) This bit is cleared when the SSP module is disabled, or when the Start bit is detected last. SSPEN is cleared. 1 = Indicates that a Stop bit has been detected last (this bit is `0' on Reset) 0 = Stop bit was not detected last S: Start bit (I2CTM mode only) This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last. SSPEN is cleared. 1 = Indicates that a Start bit has been detected last (this bit is `0' on Reset) 0 = Start bit was not detected last R/W: Read/Write bit Information (I2CTM mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2CTM mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only): 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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PIC16CR7X
REGISTER 9-2:
R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
SSPCON: SYNC SERIAL PORT CONTROL (ADDRESS 14h)
R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit In SPI mode: 1 = Enables serial port and configures SCK, SDO and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level (Microwire default) 0 = Idle state for clock is a low level (Microwire alternate) In I2 C mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2CTM Slave mode, 7-bit address 0111 = I2CTM Slave mode, 10-bit address 1011 = I2CTM Firmware Controlled Master mode (slave Idle) 1110 = I2CTM Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2CTM Slave mode, 10-bit address with Start and Stop bit interrupts enabled
bit 6
bit 5
bit 4
bit 3-0
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
FIGURE 9-1: SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF Reg Write
To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is: * SDI must have TRISC<4> set * SDO must have TRISC<5> cleared * SCK (Master mode) must have TRISC<3> cleared * SCK (Slave mode) must have TRISC<3> set * SS must have TRISA<5> set and ADCON must be configured such that RA5 is a digital I/O
SSPSR Reg RC4/SDI/SDA RC5/SDO bit 0 Shift Clock
Peripheral OE
SS Control Enable RA5/SS/AN4 Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select RC3/SCK/ SCL TRISC<3> TMR2 Output 2 Prescaler TCY 4, 16, 64
Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE = `1', then the SS pin control must be enabled. 3: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = `0100'), the state of the SS pin can affect the state read back from the TRISC<5> bit. The Peripheral OE signal from the SSP module into PORTC controls the state that is read back from the TRISC<5> bit (see Section 4.3 "PORTC and the TRISC Register" for information on PORTC). If Read-Modify-Write instructions, such as BSF are performed on the TRISC register while the SS pin is high, this will cause the TRISC<5> bit to be set, thus disabling the SDO output.
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PIC16CR7X
FIGURE 9-2:
SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO SDI (SMP = 0) bit 7 SDI (SMP = 1) bit 7 SSPIF bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE TIMING, MASTER MODE
FIGURE 9-3:
SS (optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SCK (CKP = 0) SCK (CKP = 1)
SDO SDI (SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7 SSPIF
bit 0
(c) 2007 Microchip Technology Inc.
DS21993C-page 63
PIC16CR7X
FIGURE 9-4:
SS
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0) SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0) bit 7 SSPIF bit 0
TABLE 9-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 GIE PSPIF(1) PSPIE(1) Bit 6 PEIE ADIF ADIE Bit 5 Bit 4 Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on all other Resets
0Bh,8Bh. INTCON 10Bh,18Bh 0Ch 8Ch 87h 13h 14h 85h 94h Legend: Note 1: PIR1 PIE1 TRISC SSPBUF
TMR0IE INTE RCIF RCIE TXIF TXIE
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 UA BF 0000 0000 0000 0000
PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register SSPOV SSPEN -- CKE CKP SSPM3 SSPM2
SSPCON WCOL TRISA SSPSTAT -- SMP
PORTA Data Direction Register D/A P S R/W
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
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PIC16CR7X
9.3 SSP I2 CTM Operation
The SSP module in I2C mode fully implements all slave functions except general call support, and provides interrupts on Start and Stop bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The SSP module functions are enabled by setting SSP enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I 2C Slave mode (10-bit address), with Start and Stop bit interrupts enabled to support Firmware Master mode * I 2C Start and Stop bit interrupts enabled to support Firmware Master mode, Slave is Idle Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. Additional information on SSP I 2C operation can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
FIGURE 9-5:
SSP BLOCK DIAGRAM (I2CTM MODE)
Internal Data Bus Read SSPBUF Reg Shift Clock SSPSR Reg Write
RC3/SCK/SCL
9.3.1
SLAVE MODE
RC4/ SDI/ SDA
MSb
LSb Addr Match
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. There are certain conditions that will cause the SSP module not to give this ACK pulse. They include (either or both): a) The Buffer Full bit BF (SSPSTAT<0>) was set before the transfer was received. The overflow bit SSPOV (SSPCON<6>) was set before the transfer was received.
Match Detect
SSPADD Reg Start and Stop bit Detect Set, Reset S, P bits (SSPSTAT Reg)
The SSP module has five registers for These are the: * * * *
I2C
operation.
b)
SSP Control Register (SSPCON) SSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) SSP Shift Register (SSPSR) - Not directly accessible * SSP Address Register (SSPADD)
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirements of the SSP module, are shown in timing parameter #100 and parameter #101.
(c) 2007 Microchip Technology Inc.
DS21993C-page 65
PIC16CR7X
9.3.1.1 Addressing
Once the SSP module has been enabled, it waits for a Start condition to occur. Following the Start condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The Buffer Full bit, BF is set. An ACK pulse is generated. SSP Interrupt Flag bit, SSPIF (PIR1<3>) is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. The sequence of events for 10-bit address is as follows, with steps 7-9 for slave-transmitter: 1. 2. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF and UA are set). Update the SSPADD register with the first (high) byte of address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated Start condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
3. 4. 5.
6. 7. 8. 9.
In 10-bit Address mode, two address bytes need to be received by the slave (Figure 9-7). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address.
TABLE 9-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Yes No No Generate ACK Pulse Yes No No Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes
Status Bits as Data Transfer is Received BF 0 1 1 0 Note: SSPOV 0 0 1
1 No No Yes Shaded cells show the conditions where the user software did not properly clear the overflow condition.
9.3.1.2
Reception
When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user's firmware. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
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PIC16CR7X
FIGURE 9-6: I 2CTM WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address SDA R/W=0 ACK Receiving Data Receiving Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8
SCL
S
9
SSPIF (PIR1<3>)
Cleared in software
Bus Master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
9.3.1.3
Transmission
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-7).
An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then monitors for another occurrence of the Start bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/ SCK/SCL should be enabled by setting bit CKP.
FIGURE 9-7:
I 2CTM WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data in sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>)
Cleared in software
SSPBUF is written in software CKP (SSPCON<4>)
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
(c) 2007 Microchip Technology Inc.
DS21993C-page 67
PIC16CR7X
9.3.2 MASTER MODE 9.3.3 MULTI-MASTER MODE
Master mode of operation is supported in firmware using interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle and both the S and P bits are clear. In Master mode, the SCL and SDA lines are manipulated by clearing the corresponding TRISC<4:3> bit(s). The output level is always low, irrespective of the value(s) in PORTC<4:3>. So when transmitting data, a `1' data bit must have the TRISC<4> bit set (input) and a `0' data bit must have the TRISC<4> bit cleared (output). The same scenario is true for the SCL line with the TRISC<3> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled): * Start condition * Stop condition * Data transfer byte transmitted/received Master mode of operation can be done with either the Slave mode Idle (SSPM3:SSPM0 = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt. In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions, allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the SSP module is disabled. The Stop (P) and Start (S) bits will toggle based on the Start and Stop conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is Idle and both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the Stop condition occurs. In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are: * Address Transfer * Data Transfer When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to retransfer the data at a later time.
TABLE 9-3:
Address
REGISTERS ASSOCIATED WITH I2CTM OPERATION
Name Bit 7 GIE PSPIF(1) PSPIE
(1)
Bit 6 PEIE ADIF ADIE
Bit 5 TMR0IE RCIF RCIE
Bit 4 INTE TXIF TXIE
Bit 3 RBIE
Bit 2 TMR0IF
Bit 1 INTF
Bit 0 RBIF
Value on POR, BOR 0000 000x 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111
Value on all other Resets 0000 000u 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 13h 93h 14h 94h 87h Legend: Note 1: 2: PIR1 PIE1
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register SSPADD Synchronous Serial Port SSPCON SSPSTAT TRISC WCOL SMP(2) (I2CTM mode) Address Register CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
SSPOV SSPEN CKE(2) D/A
PORTC Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in I2CTM mode. PSPIF and PSPIE are reserved on the PIC16CR73/76; always maintain these bits clear. Maintain these bits clear in I2C mode.
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PIC16CR7X
10.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/ RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 10-1:
R/W-0 CSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7
TXSTA: TRANSMIT STATUS AND CONTROL (ADDRESS 98h)
R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
CSRC: Clock Source Select bit Asynchronous mode: Don't care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data Can be parity bit
bit 6
bit 5
bit 4
bit 3 bit 2
bit 1
bit 0
(c) 2007 Microchip Technology Inc.
DS21993C-page 69
PIC16CR7X
REGISTER 10-2:
R/W-0 SPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
RCSTA: RECEIVE STATUS AND CONTROL (ADDRESS 18h)
R/W-0 RX9 R/W-0 SREN R/W-0 CREN U-0 -- R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care
bit 6
bit 5
bit 4
CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive Unimplemented: Read as `0' FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data Can be parity bit (parity to be calculated by firmware)
bit 3 bit 2
bit 1
bit 0
DS21993C-page 70
(c) 2007 Microchip Technology Inc.
PIC16CR7X
10.1 USART Baud Rate Generator (BRG)
It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for different USART modes which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 10-1. From this, the error in baud rate can be determined.
10.1.1
SAMPLING
The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 10-1:
SYNC 0 1
BAUD RATE FORMULA
BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) N/A
X = value in SPBRG (0 to 255)
TABLE 10-2:
Address 98h 18h 99h
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN Bit 4 SYNC Bit 3 -- -- Bit 2 BRGH FERR Bit 1 Bit 0 Value on POR, BOR Value on all other Resets
0000 -010 0000 -00x 0000 0000
Name TXSTA RCSTA
SREN CREN
TRMT TX9D 0000 -010 OERR RX9D 0000 -00x
0000 0000
SPBRG Baud Rate Generator Register
Legend: x = unknown, - = unimplemented, read as `0'. Shaded cells are not used by the BRG.
(c) 2007 Microchip Technology Inc.
DS21993C-page 71
PIC16CR7X
TABLE 10-3:
BAUD RATE BAUD 1200 2400 9600 19,200 38,400 57,600 76,800 96,000 115,200 250,000 1,221 2,404 9,470 19,531 39,063 62,500 78,125 104,167 104,167 312,500
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz % ERROR 1.73% 0.16% -1.36% 1.73% 1.73% 8.51% 1.73% 8.51% -9.58% 25.00% SPBRG VALUE (DECIMAL) 255 129 32 15 7 4 3 2 2 0 FOSC = 16 MHz % ERROR 0.16% 0.16% 0.16% 0.16% -6.99% 8.51% 8.51% -13.19% 8.51% 0.00% SPBRG VALUE (DECIMAL) 207 103 25 12 6 3 2 2 1 0 FOSC = 10 MHz % ERROR 0.16% 0.16% 1.73% 1.73% 1.73% -9.58% 1.73% -18.62% -32.18% -37.50% SPBRG VALUE (DECIMAL) 129 64 15 7 3 2 1 1 1 0
BAUD 1,202 2,404 9,615 19,231 35,714 62,500 83,333 83,333 125,000 250,000
BAUD 1,202 2,404 9,766 19,531 39,063 52,083 78,125 78,125 78,125 156,250
FOSC = 4 MHz BAUD RATE BAUD 300 1200 2400 9600 19,200 38,400 57,600 76,800 300 1,202 2,404 8,929 20,833 31,250 62,500 62,500 % ERROR 0.16% 0.16% 0.16% -6.99% 8.51% -18.62% 8.51% -18.62% SPBRG VALUE (DECIMAL) 207 51 25 6 2 1 0 0
FOSC = 3.6864 MHz % ERROR 0.00% 0.00% 0.00% 0.00% 0.00% -25.00% 0.00% -- SPBRG VALUE (DECIMAL) 191 47 23 5 2 1 0 --
FOSC = 3.579545 MHz % ERROR 0.23% -0.83% 1.32% -2.90% -2.90% -27.17% -2.90% -- SPBRG VALUE (DECIMAL) 185 46 22 5 2 1 0 --
BAUD 300 1,200 2,400 9,600 19,200 28,800 57,600 --
BAUD 301 1,190 2,432 9,322 18,643 27,965 55,930 --
TABLE 10-4:
BAUD RATE BAUD 2400 9600 19,200 38,400 57,600 76,800 96,000 115,200 250,000 300,000 -- 9,615 19,231 37,879 56,818 78,125 96,154 113,636 250,000 312,500
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz % ERROR -- 0.16% 0.16% -1.36% -1.36% 1.73% 0.16% -1.36% 0.00% 4.17% FOSC = 4 MHz SPBRG VALUE (DECIMAL) -- 129 64 32 21 15 12 10 4 3 FOSC = 16 MHz % ERROR -- 0.16% 0.16% 0.16% 2.12% 0.16% 4.17% -3.55% 0.00% 11.11% FOSC = 3.6864 MHz SPBRG VALUE (DECIMAL) 207 103 25 12 6 3 2 2 1 0 % ERROR 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 0.00% 20.00% 0.00% -7.84% SPBRG VALUE (DECIMAL) 191 95 23 11 5 3 2 1 1 0 SPBRG VALUE (DECIMAL) -- 103 51 25 16 12 9 8 3 2 FOSC = 10 MHz % ERROR 1.73% 0.16% -1.36% 1.73% -1.36% 1.73% -6.99% 8.51% -16.67% 4.17% FOSC = 3.579545 MHz % ERROR 0.23% 0.23% 1.32% -2.90% -2.90% -2.90% -2.90% 16.52% -2.90% -10.51% SPBRG VALUE (DECIMAL) 185 92 22 11 5 3 2 1 1 0 SPBRG VALUE (DECIMAL) 255 64 32 15 10 7 6 4 2 1
BAUD -- 9,615 19,231 38,462 58,824 76,923 100,000 111,111 250,000 333,333
BAUD 2,441 9,615 18,939 39,063 56,818 78,125 89,286 125,000 208,333 312,500
BAUD RATE (K) 1200 2400 9600 19,200 38,400 57,600 76,800 96,000 115,200 250,000
BAUD 1,202 2,404 9,615 19,231 35,714 62,500 83,333 83,333 125,000 250,000
% ERROR 0.16% 0.16% 0.16% 0.16% -6.99% 8.51% 8.51% -13.19% 8.51% 0.00%
BAUD 1,200 2,400 9,600 19,200 38,400 57,600 76,800 115,200 115,200 230,400
BAUD 1,203 2,406 9,727 18,643 37,287 55,930 74,574 111,861 111,861 223,722
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(c) 2007 Microchip Technology Inc.
PIC16CR7X
10.2 USART Asynchronous Mode
Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RC6/TX/CK pin will revert to high-impendance. In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. In this mode, the USART uses standard non-return-tozero (NRZ) format (one Start bit, eight or nine data bits, and one Stop bit). The most common data format is 8bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during Sleep. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver
10.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data by firmware. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register, the TXREG register is empty. One instruction cycle later, flag bit TXIF (PIR1<4>) and flag bit TRMT (TXSTA<1>) are set. The TXIF interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read-only bit, which is set one instruction cycle after the TSR register becomes empty, and is cleared one instruction cycle after the TSR register is loaded. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty.
(c) 2007 Microchip Technology Inc.
DS21993C-page 73
PIC16CR7X
FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN TXREG Register 8 *** TSR Register LSb 0 Pin Buffer and Control RC6/TX/CK pin
Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9.
5. 6. 7. 8.
2. 3. 4.
Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
FIGURE 10-2:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Transmit Buffer Reg. Empty Flag)
ASYNCHRONOUS MASTER TRANSMISSION
Word 1
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
DS21993C-page 74
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 10-3:
Write to TXREG BRG Output (Shift Clock) RC6/TX/CK (pin) TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Word 2
ASYNCHRONOUS MASTER TRANSMISSION (BACK-TO-BACK)
Start bit
bit 0
bit 1 Word 1
bit 7/8
Stop bit
Start bit Word 2
bit 0
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
Note: This timing diagram shows two consecutive transmissions.
TABLE 10-5:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7
GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 RBIF TMR1IF RX9D TMR1IE TX9D Value on POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 SSPIE CCP1IE -- BRGH 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA TXREG PIE1 TXSTA
USART Transmit Data Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear.
10.2.2
USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the Receive (serial) Shift Register (RSR). After sampling the Stop bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read-only bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full, the overrun error bit OERR (RCSTA<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited and no further data will be received, therefore, it is essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a Stop bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading RCREG register, in order not to lose the old FERR and RX9D information.
(c) 2007 Microchip Technology Inc.
DS21993C-page 75
PIC16CR7X
FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN FOSC SPBRG Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery RX9 /64 or /16 MSb Stop (8) 7 RSR Register *** 1 LSb 0 Start OERR FERR
SPEN
RX9D
RCREG Register
FIFO
8 Interrupt RCIF RCIE Data Bus
FIGURE 10-5:
RX (pin) Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note:
ASYNCHRONOUS RECEPTION
Start bit bit 0 bit 1 bit 7/8 Stop bit Start bit bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit
Word 1 RCREG
Word 2 RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.
Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.
Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
8.
2. 3. 4. 5. 6.
7.
DS21993C-page 76
(c) 2007 Microchip Technology Inc.
PIC16CR7X
TABLE 10-6:
Address Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 TMR0IE RCIF SREN Bit 4 INTE TXIF CREN Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D Value on POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 TXIE SYNC SSPIE -- CCP1IE BRGH TMR2IE TRMT TMR1IE TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Register ADIE TX9 RCIE TXEN
Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
(c) 2007 Microchip Technology Inc.
DS21993C-page 77
PIC16CR7X
10.3 USART Synchronous Master Mode
Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to highimpendance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a high-impendance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from High-Impendance Receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a Synchronous Master Transmission: 1. Initialize the SPBRG register for the appropriate baud rate (Section 10.1 "USART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).
10.3.1
USART SYNCHRONOUS MASTER TRANSMISSION
The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The shift register obtains its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. TRMT is a readonly bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 10-6). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-7). This is advantageous when slow baud rates are selected, since the BRG is kept in Reset when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.
2. 3. 4. 5. 6. 7. 8.
DS21993C-page 78
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 10-6: SYNCHRONOUS TRANSMISSION
Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4
RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg TXIF bit (Interrupt Flag) TRMTTRMT bit `1'
bit 0
bit 1 Word 1
bit 2
bit 7
bit 0
bit 1 Word 2
bit 7
Write Word 1
Write Word 2
TXEN bit
`1'
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 10-7:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7
RC7/RX/DT pin RC6/TX/CK pin
Write to TXREG Reg
TXIF bit
TRMT bit
TXEN bit
TABLE 10-7:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 Bit 5 TMR0IE RCIF SREN Bit 4 INTE TXIF CREN Bit 3 RBIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF TMR1IF RX9D Value on POR, BOR 0000 000x 0000 0000 0000 -00x 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE -- BRGH TRMT TX9D 0000 0000 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
SSPIF CCP1IF TMR2IF -- FERR OERR
USART Transmit Data Register ADIE TX9 RCIE TXEN TXIE SYNC
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
(c) 2007 Microchip Technology Inc.
DS21993C-page 79
PIC16CR7X
10.3.2 USART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read-only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a twodeep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 10.1 "USART Baud Rate Generator (BRG)"). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
FIGURE 10-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG `0'
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
DS21993C-page 80
(c) 2007 Microchip Technology Inc.
PIC16CR7X
TABLE 10-8:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF Value on POR, BOR 0000 000x Value on all other Resets 0000 000u 0000 0000 0000 -00x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
TMR1IF 0000 0000 RX9D 0000 -00x 0000 0000
USART Receive Data Register -- BRGH TRMT TX9D
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 -010 0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
10.4
USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).
Follow these steps when setting up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
2. 3. 4. 5. 6. 7. 8.
10.4.1
USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes are identical except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) The first word will immediately transfer to the TSR register and transmit when the master device drives the CK line. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set. If enable bit TXIE is set, the interrupt will wake the chip from Sleep and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
b) c) d)
e)
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TABLE 10-9:
Address
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA PIE1 TXSTA
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
TXREG USART Transmit Data Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices; always maintain these bits clear.
10.4.2
USART SYNCHRONOUS SLAVE RECEPTION
Follow these steps when setting up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE in the INTCON register are set.
The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. Bit SREN is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 GIE PSPIF(1) SPEN PSPIE(1) CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 RBIF TMR1IF RX9D Value on POR, BOR 0000 000x 0000 0000 0000 000x 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other Resets 0000 000u 0000 0000 0000 000x 0000 0000 0000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: Note 1: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Data Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception. Bits PSPIE and PSPIF are reserved on the PIC16CR73/76 devices, always maintain these bits clear.
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PIC16CR7X
11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has three registers. These registers are: * A/D Result Register ((ADRES) * A/D Control Register 0 (ADCON0) * A/D Control Register 1 ((ADCON1) The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured as analog inputs (RA3 can also be a voltage reference), or as digital I/O. Additional information on using the A/D module can be found in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023) and in Application Note AN546, "Using The Analog-to-Digital Converter" (DS00546).
The 8-bit Analog-to-Digital (A/D) converter module has five inputs for the PIC16CR73/76 and eight for the PIC16CR74/77. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device's positive supply voltage (VDD), or the voltage level on the RA3/AN3/VREF pin. The A/D converter has a unique feature of being able to operate while the device is in Sleep mode. To operate in Sleep, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
REGISTER 11-1:
R/W-0 ADCS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6
ADCON0: (ADDRESS 1Fh)
R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) CHS2:CHS0: Analog Channel Select bits 000 = Channel 0 (RA0/AN0) 001 = Channel 1 (RA1/AN1) 010 = Channel 2 (RA2/AN2) 011 = Channel 3 (RA3/AN3) 100 = Channel 4 (RA5/AN4) 101 = Channel 5 (RE0/AN5)(1) 110 = Channel 6 (RE1/AN6)(1) 111 = Channel 7 (RE2/AN7)(1) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 =A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) Unimplemented: Read as `0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Note: A/D channels 5, 6 and 7 are implemented on the PIC16CR74/77 only.
bit 5-3
bit 2
bit 1 bit 0
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PIC16CR7X
REGISTER 11-2:
U-0 -- bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
ADCON1: (ADDRESS 1Fh)
U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0
Unimplemented: Read as `0' PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 000 001 010 011 100 101 11x A = Analog input D = Digital I/O RA0 A A A A A A D RA1 A A A A A A D RA2 A A A A D D D RA5 A A A A D D D RA3 A VREF A VREF A VREF D RE0(1) RE1(1) RE2(1) A A D D D D D A A D D D D D A A D D D D D VREF VDD RA3 VDD RA3 VDD RA3 VDD
Note 1:
RE0, RE1 and RE2 are implemented on the PIC16CR74/77 only.
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PIC16CR7X
The following steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) Configure the A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set PEIE bit * Set GIE bit Select an A/D input channel (ADCON0). 4. 5. 6. Wait for at least an appropriate acquisition period. Start conversion: * Set GO/DONE bit (ADCON0) Wait for the A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (interrupts disabled) OR 7. 8. * Waiting for the A/D interrupt Read A/D Result register (ADRES) and clear bit ADIF if required. For next conversion, go to step 3 or step 4, as required.
2.
3.
FIGURE 11-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
111 110 101 100 VIN (Input Voltage) 011 010 A/D Converter 001
RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4 RA3/AN3/VREF RA2/AN2 RA1/AN1
VREF (Reference Voltage)
VDD 000 or 010 or 100 or 11x 001 or 011 or 101 PCFG2:PCFG0
000 RA0/AN0
Note 1: Not available on PIC16CR73/76.
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PIC16CR7X
11.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2. The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 k. After the analog input channel is selected (changed), the acquisition period must pass before the conversion can be started. To calculate the minimum acquisition time, TACQ, see the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). In general, however, given a maximum source impedance of 10 k and at a temperature of 100C, TACQ will be no more than 16 sec.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD ANx VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC Capacitance = 51.2 pF VSS Legend: CPIN VT = input capacitance = threshold voltage
RS
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
I leakage = leakage current at the pin due to various junctions RIC SS CHOLD = interconnect resistance = sampling switch = sample/hold capacitance (from DAC)
6V 5V VDD 4V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
TABLE 11-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD) Maximum Device Frequency Max. 1.25 MHz 5 MHz 20 MHz (Note 1)
Operation 2TOSC 8TOSC 32TOSC RC(1, 2, 3)
ADCS1:ADCS0 00 01 10 11
Note 1: The RC source has a typical TAD time of 4 s but can vary between 2-6 s. 2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for Sleep operation. 3: For extended voltage devices (LC), please refer to the Electrical Specifications section.
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PIC16CR7X
11.2 Selecting the A/D Conversion Clock
Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be changed and the ADIF flag will not be set. After the GO/DONE bit is cleared at either the end of a conversion, or by firmware, another conversion can be initiated by setting the GO/DONE bit. Users must still take into account the appropriate acquisition time for the application.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The four possible options for TAD are: * * * * 2 TOSC (FOSC/2) 8 TOSC (FOSC/8) 32 TOSC (FOSC/32) Internal RC oscillator (2-6 s)
11.5
A/D Operation During Sleep
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time as small as possible, but no less than 1.6 s.
11.3
Configuring Analog Port Pins
The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. Note 1: When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input, but not as an analog input, may cause the digital input buffer to consume current that is out of the device's specification.
The A/D module can operate during Sleep mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from Sleep. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in Sleep, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in Sleep, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit.
11.6
Effects of a Reset
11.4
Note:
A/D Conversions
The GO/DONE bit should NOT be set in the same instruction that turns on the A/D.
A device Reset forces all registers to their Reset state. The A/D module is disabled and any conversion in progress is aborted. All A/D input pins are configured as analog inputs. The ADRES register will contain unknown data after a Power-on Reset.
Setting the GO/DONE bit begins an A/D conversion. When the conversion completes, the 8-bit result is placed in the ADRES register, the GO/DONE bit is cleared, and the ADIF flag (PIR<6>) is set. If both the A/D interrupt bit ADIE (PIE1<6>) and the peripheral interrupt enable bit PEIE (INTCON<6>) are set, the device will wake from Sleep whenever ADIF is set by hardware. In addition, an interrupt will also occur if the Global Interrupt bit GIE (INTCON<7>) is set.
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PIC16CR7X
11.7 Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input channel must be selected and an appropriate acquisition time should pass before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 11-2:
Address
SUMMARY OF A/D REGISTERS
Bit 7 GIE PSPIF(1) -- PSPIE -- ADCS1 -- -- -- -- IBF
(1)
Name
Bit 6 PEIE ADIF -- ADIE -- ADCS0 -- -- -- -- OBF
Bit 5 TMR0IE RCIF -- RCIE -- CHS2 -- RA5 -- IBOV
Bit 4 INTE TXIF -- TXIE -- CHS1 -- RA4 -- PSPMODE
Bit 3 RBIE SSPIF -- SSPIE --
Bit 2 TMR0IF CCP1IF -- CCP1IE --
Bit 1 INTF
Bit 0 RBIF
Value on POR, BOR
Value on all other Resets
0Bh,8Bh, INTCON 10Bh, 18Bh 0Ch 0Dh 8Ch 8Dh 1Eh 1Fh 9Fh 05h 85h 09h 89h Legend: PIR1 PIR2 PIE1 PIE2 ADRES ADCON0 ADCON1 PORTA TRISA PORTE(2) TRISE(2)
0000 000x 0000 000u
TMR2IF TMR1IF 0000 0000 0000 0000 -- -- -- PCFG1 RA1 RE1 CCP2IF ---- ---0 ---- ---0 CCP2IE ---- ---0 ---- ---0 xxxx xxxx uuuu uuuu ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 RA0 RE0 --0x 0000 --0u 0000 --11 1111 --11 1111 ---- -xxx ---- -uuu 0000 -111 0000 -111 TMR2IE TMR1IE 0000 0000 0000 0000
A/D Result Register Byte CHS0 GO/DONE -- RA3 -- -- PCFG2 RA2 RE2
PORTA Data Direction Register
PORTE Data Direction Bits
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for A/D conversion.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16CR73/76; always maintain these bits clear. 2: These registers are reserved on the PIC16CR73/76.
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PIC16CR7X
12.0 SPECIAL FEATURES OF THE CPU
Sleep mode is designed to offer a very low-current power-down mode. The user can wake-up from Sleep through external Reset, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. Configuration bits are used to select the desired oscillator mode. Additional information on special features is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: * Oscillator Selection * Reset - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Sleep * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM These devices have a Watchdog Timer, which can be enabled or disabled, using a Configuration bit. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in Reset while the power supply stabilizes, and is enabled or disabled, using a Configuration bit. With these two timers on-chip, most applications need no external Reset circuitry.
12.1
Configuration Bits
The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped in program memory location 2007h. The user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
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PIC16CR7X
REGISTER 12-1:
U-0 -- bit 13 R/P-1 BOREN bit 6 Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-0 -- R/P-1 CP0 R/P-1 PWRTEN R/P-1 WDTEN R/P-1 FOSC1
CONFIGURATION WORD: (ADDRESS 2007h(1))
U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 7 R/P-1 FOSC0 bit 0
bit 13-7 bit 6
Unimplemented: Read as `1' BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled Unimplemented: Read as `1' CP0: ROM Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator The erased (unprogrammed) value of the Configuration Word is 3FFFh.
bit 5 bit 4
bit 3
bit 2
bit 1-0
Note 1:
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PIC16CR7X
12.2
12.2.1
Oscillator Configurations
OSCILLATOR TYPES
FIGURE 12-2:
EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION)
The PIC16CR7X can be operated in four different oscillator modes. The user can program two Configuration bits (FOSC1 and FOSC0) to select one of these four modes: * * * * LP XT HS RC Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator Resistor/Capacitor
Clock from Ext. System Open
OSC1 PIC16CR7X (HS Mode) OSC2
12.2.2
CRYSTAL OSCILLATOR/CERAMIC RESONATORS
TABLE 12-1:
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 12-1). The PIC16CR7X oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in HS mode, the device can accept an external clock source to drive the OSC1/CLKIN pin (Figure 12-2). See Figure 15-1 or Figure 15-2 (depending on the part number and VDD range) for valid external clock frequencies.
CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY)
Typical Capacitor Values Used: Mode XT Freq. 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 56 pF 47 pF 33 pF 27 pF 22 pF OSC2 56 pF 47 pF 33 pF 27 pF 22 pF
HS
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes at the bottom of page 92 for additional information. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX
FIGURE 12-1:
CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)
OSC1 To Internal Logic SLEEP PIC16CR7X
C1(1)
XTAL OSC2 RS(2) C2(1) Note 1: 2: 3:
RF(3)
See Table 12-1 and Table 12-2 recommended values of C1 and C2.
for
A series resistor (RS) may be required for AT strip cut crystals. RF varies with the crystal chosen.
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PIC16CR7X
TABLE 12-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY)
Crystal Freq. 32 kHz 200 kHz XT 200 kHz 1 MHz 4 MHz HS 4 MHz 8 MHz 20 MHz Typical Capacitor Values Tested: C1 LP 33 pF 15 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF C2 33 pF 15 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF
VDD REXT OSC1 CEXT VSS FOSC/4 Recommended values: OSC2/CLKOUT 3 k REXT 100 k CEXT > 20pF Internal Clock PIC16CR7X
12.2.3
RC OSCILLATOR
Osc Type
For timing insensitive applications, the "RC" device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 12-3 shows how the R/C combination is connected to the PIC16CR7X.
FIGURE 12-3:
RC OSCILLATOR MODE
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 32 kHz 200 kHz 1 MHz 4 MHz 8 MHz 20 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C
Note 1: Higher capacitance increases the stability of oscillator, but also increases the startup time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
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PIC16CR7X
12.3 Reset
The PIC16CR7X differentiates between various kinds of Reset: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset (during normal operation) WDT Wake-up (during Sleep) Brown-out Reset (BOR) Some registers are not affected in any Reset condition. Their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a "Reset state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during Sleep, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 12-4. These bits are used in software to determine the nature of the Reset. See Table 12-6 for a full description of Reset states of all registers. A simplified block diagram of the on-chip Reset circuit is shown in Figure 12-4.
FIGURE 12-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR Sleep WDT Module VDD Rise Detect VDD Brown-out Reset BODEN OST/PWRT OST 10-bit Ripple Counter OSC1 (1) On-chip RC OSC Chip_Reset R Q Power-on Reset S WDT Time-out Reset
PWRT 10-bit Ripple Counter
Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
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PIC16CR7X
12.4 MCLR 12.6 Power-up Timer (PWRT)
PIC16CR7X devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of an RC network, as shown in Figure 12-5, is suggested. The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in Reset as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A Configuration bit is provided to enable/disable the PWRT. The power-up time delay will vary from chip-to-chip, due to VDD, temperature and process variation. See DC parameters for details (TPWRT, parameter #33).
12.7
Oscillator Start-up Timer (OST)
FIGURE 12-5:
VDD
RECOMMENDED MCLR CIRCUIT
PIC16CR7X
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT delay is over (if enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or wake-up from Sleep.
R1 1 k (or greater) MCLR C1 0.1 F (optional, not critical)
12.8
Brown-out Reset (BOR)
The Configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100 S), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a Reset may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in Reset for TPWRT (parameter #33, about 72 mS). If VDD should fall below VBOR during TPWRT, the Brown-out Reset process will restart when VDD rises above VBOR, with the Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT Configuration bit.
12.5
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V-1.7V). To take advantage of the POR, tie the MCLR pin to VDD as described in Section 12.4 "MCLR". A maximum rise time for VDD is specified. See the Electrical Specifications for details. When the device starts normal operation (exits the Reset condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. For additional information, refer to Application Note AN607, "Power-up Trouble Shooting" (DS00607).
12.9
Time-out Sequence
On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR Reset occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of Reset. If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16CR7X device operating in parallel. Table 12-5 shows the Reset conditions for the STATUS, PCON and PC registers, while Table 12-6 shows the Reset conditions for all the registers.
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PIC16CR7X
12.10 Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has two bits to indicate the type of Reset that last occurred. Bit 0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. Bit 1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 12-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 72 ms + 1024 TOSC 72 ms PWRTE = 1 1024 TOSC -- Brown-out 72 ms + 1024 TOSC 72 ms Wake-up from Sleep 1024 TOSC --
Oscillator Configuration XT, HS, LP RC
TABLE 12-4:
STATUS BITS AND THEIR SIGNIFICANCE
Significance Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during Sleep or interrupt wake-up from Sleep
POR BOR TO PD (PCON<1>) (PCON<0>) (STATUS<4>) (STATUS<3>) 0 0 0 1 1 1 1 1 x x x 0 1 1 1 1 1 0 x 1 0 0 u 1 1 x 0 1 1 0 u 0
TABLE 12-5:
RESET CONDITION FOR SPECIAL REGISTERS
Condition Program Counter 000h 000h 000h 000h PC + 1 000h STATUS Register 0001 1xxx 000u uuuu 0001 0000 uuu0 0001 0uuu 1uuu 0uuu 1uuu PCON Register ---- --0x ---- --uu --------------uu --uu --uu --u0
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset WDT Wake-up Brown-out Reset
uuu1 0uuu ---- --uu Interrupt wake-up from Sleep PC + 1(1) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
TABLE 12-6:
Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 73 73 73 73 73 73 73 73 73 73 73 73 73 73 73
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Devices 74 74 74 74 74 74 74 74 74 74 74 74 74 74 74 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 77 77 77 77 77 77 77 77 77 77 77 77 77 77 77 Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 xxxx --0x xxxx xxxx xxxx ------0 1xxx xxxx 0000 xxxx xxxx xxxx -xxx 0000 MCLR Reset, WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q uuuu --0u uuuu uuuu uuuu ------0 quuu(3) uuuu 0000 uuuu uuuu uuuu -uuu 0000 Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq uuuu --uu uuuu uuuu uuuu ------u quuu(3) uuuu uuuu uuuu uuuu uuuu -uuu uuuu
0000 000x r000 0000 0000 0000
0000 000u r000 0000 0000 0000
uuuu uuuu(1) ruuu uuuu(1) uuuu uuuu(1)
PIR2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u(1) TMR1L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 73 74 76 77 --00 0000 --uu uuuu --uu uuuu TMR2 73 74 76 77 0000 0000 0000 0000 uuuu uuuu T2CON 73 74 76 77 -000 0000 -000 0000 -uuu uuuu SSPBUF 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu CCPR1L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 73 74 76 77 --00 0000 --00 0000 --uu uuuu RCSTA 73 74 76 77 0000 -00x 0000 -00x uuuu -uuu TXREG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu RCREG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu CCPR2L 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ADRES 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 73 74 76 77 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISA 73 74 76 77 --11 1111 --11 1111 --uu uuuu TRISB 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISC 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISD 73 74 76 77 1111 1111 1111 1111 uuuu uuuu TRISE 73 74 76 77 0000 -111 0000 -111 uuuu -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for Reset value for specific condition.
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PIC16CR7X
TABLE 12-6:
Register PIE1 73 73
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Devices 74 74 76 76 77 77 Power-on Reset, Brown-out Reset r000 0000 0000 0000 MCLR Reset, WDT Reset r000 0000 0000 0000 Wake-up via WDT or Interrupt ruuu uuuu uuuu uuuu
PIE2 73 74 76 77 ---- ---0 ---- ---0 ---- ---u PCON 73 74 76 77 ---- --qq ---- --uu ---- --uu PR2 73 74 76 77 1111 1111 1111 1111 1111 1111 SSPSTAT 73 74 76 77 --00 0000 --00 0000 --uu uuuu SSPADD 73 74 76 77 0000 0000 0000 0000 uuuu uuuu TXSTA 73 74 76 77 0000 -010 0000 -010 uuuu -uuu SPBRG 73 74 76 77 0000 0000 0000 0000 uuuu uuuu ADCON1 73 74 76 77 ---- -000 ---- -000 ---- -uuu PMDATA 73 74 76 77 0--- 0000 0--- 0000 u--- uuuu PMADR 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMDATH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMADRH 73 74 76 77 xxxx xxxx uuuu uuuu uuuu uuuu PMCON1 73 74 76 77 1--- ---0 1--- ---0 1--- ---u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 12-5 for Reset value for specific condition.
FIGURE 12-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK)
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
FIGURE 12-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-8:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-9:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V VDD MCLR 0V 1V
INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET
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PIC16CR7X
12.11 Interrupts
The PIC16CR7X family has up to 12 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Registers, PIR1 and PIR2. The corresponding interrupt enable bits are contained in Special Function Registers, PIE1 and PIE2, and the peripheral interrupt enable bit is contained in Special Function Register, INTCON. When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs, relative to the current Q cycle. The latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit.
A Global Interrupt Enable bit, GIE (INTCON<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set, regardless of the status of the GIE bit. The GIE bit is cleared on Reset. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.
FIGURE 12-10:
PSPIF(1) PSPIE(1) ADIF ADIE
INTERRUPT LOGIC
TMR0IF TMR0IE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE INTF INTE RBIF RBIE PEIE GIE
Wake-up (If in Sleep mode)
Interrupt to CPU
TMR1IF TMR1IE CCP2IF CCP2IE
Note 1:
PSP interrupt is implemented only on PIC16CR74/77 devices.
(c) 2007 Microchip Technology Inc.
DS21993C-page 99
PIC16CR7X
12.11.1 INT INTERRUPT
12.12 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W, PCLATH and STATUS registers). This will have to be implemented in software, as shown in Example 12-1. For the PIC16CR73/74 devices, the register W_TEMP must be defined in both banks 0 and 1 and must be defined at the same offset from the bank base address (i.e., If W_TEMP is defined at 20h in bank 0, it must also be defined at A0h in bank 1.). The registers, PCLATH_TEMP and STATUS_TEMP, are only defined in bank 0. Since the upper 16 bytes of each bank are common in the PIC16CR76/77 devices, temporary holding registers W_TEMP, STATUS_TEMP and PCLATH_TEMP should be placed in here. These 16 locations don't require banking and, therefore, make it easier for context save and restore. The same code shown in Example 12-1 can be used.
External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION_REG<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from Sleep, if bit INTE was set prior to going into Sleep. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 12.14 "Power-down Mode (Sleep)" for details on Sleep mode.
12.11.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>). (Section 5.0 "Timer0 Module")
12.11.3
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<3>), see Section 4.2 "PORTB and the TRISB Register".
EXAMPLE 12-1:
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF
SAVING STATUS, W AND PCLATH REGISTERS IN RAM
;Copy ;Swap ;bank ;Save ;Only ;Save ;Page W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register required if using pages 1, 2 and/or 3 PCLATH into W zero, regardless of current page
W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH
;Insert user code here PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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PIC16CR7X
12.13 Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device Reset (Watchdog Timer Reset). If the device is in Sleep mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out. The WDT can be permanently disabled by clearing Configuration bit, WDTE (Section 12.1 "Configuration Bits"). WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler), may be assigned using the OPTION_REG register. Note 1: The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device Reset condition. 2: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.
FIGURE 12-11:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source (Figure 5-1) 0 WDT Timer 1 M U X Postscaler 8 8-to-1 MUX WDT Enable Bit PSA To TMR0 (Figure 5-1) PS2:PS0
0 MUX
1 PSA
WDT Time-out Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
TABLE 12-7:
Address 2007h
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 (1) RBPU Bit 6 BOREN(1) INTEDG Bit 5 -- T0CS Bit 4 CP0 T0SE Bit 3 PWRTEN(1) PSA Bit 2 WDTEN PS2 Bit 1 FOSC1 PS1 Bit 0 FOSC0 PS0
Config. bits
81h,181h OPTION_REG
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 12-1 for operation of these bits.
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
12.14 Power-down Mode (Sleep)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or high-impendance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are high-impendance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC). When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up occurs, regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
12.14.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from Sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
12.14.1
WAKE-UP FROM SLEEP
The device can wake-up from Sleep through one of the following events: 1. 2. 3. External Reset input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a Peripheral Interrupt.
External MCLR Reset will cause a device Reset. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of device Reset. The PD bit, which is set on power-up, is cleared when Sleep is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from Sleep: 1. 2. 3. 4. 5. 6. 7. 8. PSP read or write (PIC16CR74/77 only). TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode, using an external clock). SSP (Start/Stop) bit detect interrupt. SSP transmit or receive in Slave mode (SPI/I2C). USART RX or TX (Synchronous Slave mode). A/D conversion (when A/D clock source is RC).
Other peripherals cannot generate interrupts, since during Sleep, no on-chip clocks are present.
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PIC16CR7X
FIGURE 12-12:
OSC1 CLKOUT(4) INT pin INTF Flag (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 Inst(PC + 1) Sleep PC + 2 PC + 2 Inst(PC + 2) Inst(PC + 1) Dummy cycle PC + 2 0004h Inst(0004h) Dummy cycle 0005h Inst(0005h) Inst(0004h) Processor in Sleep Interrupt Latency (Note 2) TOST(2)
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
XT, HS or LP oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC osc mode. GIE = `1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = `0', execution will continue in-line. CLKOUT is not available in these osc modes, but shown here for timing reference.
12.15 Program Verification/Code Protection
If the code protection bit(s) have not been enabled, the on-chip program memory can be read out for verification purposes.
12.16 ID Locations
Four memory locations (2000h-2002h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable for program verification. It is recommended that only the 4 Least Significant bits of the ID location are used.
12.17 User Code
PIC16CR7X microcontrollers are ROM-based, thus user programming is not possible. Please contact your Microchip sales representitive for details on how to submit your final code. This information can also be found in Application Note AN1010, "PIC16CR ROM Code Submission Process".
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PIC16CR7X
NOTES:
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PIC16CR7X
13.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The formats for each of the categories are presented in Figure 13-1, while the various opcode fields are summarized in Table 13-1. Table 13-2 lists the instructions recognized by the MPASMTM Assembler. A complete description of each instruction is also available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an eight- or eleven-bit constant or literal value. One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future PIC16CR7X products, do not use the OPTION and TRIS instructions. For example, a "CLRF PORTB" instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared for pins configured as inputs and using the PORTB interrupt-on-change feature.
TABLE 13-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 13-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
13.1
Read-Modify-Write operations
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
0
k = 11-bit immediate value
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
TABLE 13-2:
Mnemonic, Operands
PIC16CR7X INSTRUCTION SET
14-Bit Opcode Description Cycles MSb BYTE-ORIENTED FILE REGISTER OPERATIONS LSb Status Affected Notes
ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF
f, d f, d f -- f, d f, d f, d f, d f, d f, d f, d f -- f, d f, d f, d f, d f, d
Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f
1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110
dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff
ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff
C,DC,Z Z Z Z Z Z Z Z Z
1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2
BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW f, b f, b f, b f, b k k k -- k k k -- k -- -- k k Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C,DC,Z Z TO,PD Z 1,2 1,2 3 3
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO,PD C,DC,Z Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. 3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the "PIC(R) Mid-Range MCU Family Reference Manual" (DS33023).
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13.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is 1, the result is stored back in register `f'. f,d
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BTFSS Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' is `0', the next instruction is executed. If bit `b' is `1', then the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
ANDWF Syntax: Operands: Operation: Status Affected: Description:
AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test f, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' is `1', the next instruction is executed. If bit `b' in register `f' is `0', the next instruction is discarded and a NOP is executed instead, making this a 2TCY instruction.
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CALL Syntax: Operands: Operation: Call Subroutine [ label ] CALL k 0 k 2047 (PC)+ 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction. Status Affected: Description: CLRWDT Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
CLRF Syntax: Operands: Operation: Status Affected: Description:
Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
COMF Syntax: Operands: Operation: Status Affected: Description:
Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' is `0', the result is stored in W. If `d' is `1', the result is stored back in register `f'. f,d
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
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DECFSZ Syntax: Operands: Operation: Status Affected: Description: Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2TCY instruction. INCFSZ Syntax: Operands: Operation: Status Affected: Description: Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2TCY instruction.
GOTO Syntax: Operands: Operation: Status Affected: Description:
Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a twocycle instruction.
IORLW Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'ed with the eight-bit literal `k'. The result is placed in the W register.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
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MOVF Syntax: Operands: Operation: Status Affected: Description: Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are moved to a destination dependant upon the status of `d'. If `d' = 0, destination is W register. If `d' = 1, the destination is file register `f' itself. `d' = 1 is useful to test a file register, since status flag Z is affected. NOP Syntax: Operands: Operation: Description: No Operation [ label ] NOP None No operation No operation.
Status Affected: None
MOVLW Syntax: Operands: Operation: Status Affected: Description:
Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The "don't cares" will assemble as `0's. MOVLW k 0 k 255
RETFIE Syntax: Operands: Operation:
Return from Interrupt [ label ] RETFIE None TOS PC, 1 GIE
Status Affected: None
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] MOVWF f 0 f 127 (W) (f) None Move data from W register to register `f'.
RETLW Syntax: Operands: Operation:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
Status Affected: None Description:
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RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is stored back in register `f'.
C Register f
SLEEP Syntax: Operands: Operation: [ label ] SLEEP None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down Status bit PD is cleared. Time-out Status bit TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped.
f,d
Status Affected: Description:
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SUBLW Syntax: Operands: Operation: Description:
Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed back in register `f'.
C Register f
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'.
Status Affected: C, DC, Z
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SWAPF Syntax: Operands: Operation: Status Affected: Description: Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' is `0', the result is placed in the W register. If `d' is `1', the result is placed in register `f'. XORWF Syntax: Operands: Operation: Status Affected: Description: Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' is `0', the result is stored in the W register. If `d' is `1', the result is stored back in register `f'. f,d
XORLW Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR Literal with W [ label ] XORLW k 0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
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14.0 DEVELOPMENT SUPPORT
14.1
The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
(c) 2007 Microchip Technology Inc.
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14.2 MPASM Assembler 14.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
14.6 14.3 MPLAB C18 and MPLAB C30 C Compilers
MPLAB SIM Software Simulator
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 family of microcontrollers and the dsPIC30, dsPIC33 and PIC24 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
14.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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14.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 14.9 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application.
14.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
14.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC(R) and MCU devices. It debugs and programs PIC(R) and dsPIC(R) Flash microcontrollers with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high speed, noise tolerant, lowvoltage differential signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
(c) 2007 Microchip Technology Inc.
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14.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
14.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart(R) battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest "Product Selector Guide" (DS00148) for the complete list of demonstration, development and evaluation kits.
14.12 PICkit 2 Development Programmer
The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers.
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15.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias................................................................................................................ .-55 to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS ........................................................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................. -0.3 to +6.5V Voltage on MCLR with respect to VSS...............................................................................................................0 to +5.5V Voltage on RA4 with respect to Vss ..................................................................................................................0 to +5.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA, PORTB, and PORTE (combined) (Note 3) ...................................................200 mA Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes at the MCLR pin may cause latch-up. A series resistor of greater than 1 k should be used to pull MCLR to VDD, rather than tying the pin directly to VDD. 3: PORTD and PORTE are not implemented on the PIC16CR73/76 devices. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 15-1: PIC16CR7X VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V 4.5V
Voltage
4.0V 3.5V 3.0V 2.5V 2.0V
16 MHz
Frequency
20 MHz
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15.1 DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions
PIC16CR73/74/76/77 (Industrial, Extended) Param No. D001 Sym VDD Characteristic Supply Voltage PIC16CR7X
2.5 2.2 2.0 4.0 VBOR* -- --
-- -- -- -- -- 1.5 VSS
5.5 5.5 5.5 5.5 5.5 -- --
V V V V V V V
A/D in use, -40C to +85C A/D in use, 0C to +85C A/D not used, -40C to +85C All configurations BOR enabled (Note 7)
D001 D001A D002* D003 VDR VPOR
PIC16CR7X RAM Data Retention Voltage (Note 1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage
See section on Power-on Reset for details
D004*
SVDD
0.05
--
--
V/ms See section on Power-on Reset for details
D005
VBOR
3.65
4.0
4.35
V
BOREN bit in Configuration Word enabled
Legend: Shading of rows is to assist in readability of of the table. * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: 2: This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impendance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
3: 4: 5: 6: 7:
(c) 2007 Microchip Technology Inc.
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PIC16CR7X
15.1 DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions PIC16CR73/74/76/77 (Industrial, Extended) Param No. D010 D010A D010 D013 D015* D020 D021 D020 D021 D021A PIC16CR7X IBOR Brown-out Reset Current (Note 6) IPD PIC16CR7X PIC16CR7X Sym IDD Characteristic Supply Current (Notes 2, 5) PIC16CR7X -- -- -- -- -- 0.5 20 1.1 6.3 30 2 48 4 15 200 mA A mA mA A XT, RC osc configuration FOSC = 4 MHz, VDD = 3.0V (Note 4) LP osc configuration FOSC = 32 kHz, VDD = 3.0V, WDT disabled XT, RC osc configuration FOSC = 4 MHz, VDD = 5.5V (Note 4) HS osc configuration FOSC = 20 MHz, VDD = 5.5V BOR enabled, VDD = 5.0V
Power-down Current (Notes 3, 5) -- -- -- -- -- -- 2.0 0.1 5 0.1 10.5 1.5 30 5 42 19 57 42 A A A A A A VDD = 3.0V, WDT enabled, -40C to +85C VDD = 3.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +85C VDD = 4.0V, WDT disabled, -40C to +85C VDD = 4.0V, WDT enabled, -40C to +125C VDD = 4.0V, WDT disabled, -40C to +125C BOR enabled, VDD = 5.0V
D023*
IBOR Brown-out Reset Current (Note 6)
--
30
200
A
Legend: Shading of rows is to assist in readability of of the table. * These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: 2: This is the limit to which VDD can be lowered without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impendance state and tied to VDD and VSS. For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. Timer1 oscillator (when enabled) adds approximately 20 A to the specification. This value is from characterization and is for design guidance only. This is not tested. The current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
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PIC16CR7X
15.2 DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 15.1 "DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)". Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Sym No. VIL D030 D030A D031 D032 D033 VIH D040 D040A D041 D042 D042A D043 D070 D060 D061 D063 * Note 1: 2: IIL
Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT and LP mode) OSC1 (in HS mode) Input High Voltage I/O ports: with TTL buffer
VSS VSS VSS VSS VSS VSS
-- -- -- -- -- --
0.15VDD 0.8V 0.2VDD 0.2VDD 0.3V 0.3VDD
V V V V V V
For entire VDD range 4.5V VDD 5.5V (Note 1)
2.0 0.25VDD + 0.8V
-- -- -- -- -- -- -- 250 -- -- --
VDD VDD VDD VDD VDD VDD VDD 400 1 5 5
V V V V V V V A A A A
4.5V VDD 5.5V For entire VDD range For entire VDD range
with Schmitt Trigger buffer MCLR OSC1 (in XT and LP mode) OSC1 (in HS mode) OSC1 (in RC mode) IPURB PORTB Weak Pull-up Current I/O ports MCLR, RA4/T0CKI OSC1
0.8VDD 0.8VDD 1.6V 0.7VDD 0.9VDD 50 -- -- --
(Note 1) VDD = 5V, VPIN = VSS Vss VPIN VDD, pin at high-impendance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration
Input Leakage Current (Notes 2, 3)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16CR7X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
3:
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PIC16CR7X
15.2 DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 15.1 "DC Characteristics: PIC16CR73/74/76/77 (Industrial, Extended)". Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Sym No. VOL D080 D083
Characteristic Output Low Voltage I/O ports OSC2/CLKOUT (RC osc config)
-- -- --
-- -- --
0.6 0.6 0.6
V V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +125C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +125C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C RA4 pin In XT, HS and LP modes when external clock is used to drive OSC1
VOH D090 D092
Output High Voltage I/O ports (Note 3) VDD - 0.7 -- -- -- -- -- -- -- -- 5.5 15 V V V V pF
OSC2/CLKOUT (RC osc config) VDD - 0.7 VDD - 0.7
D150* D100
VOD
Open Drain High Voltage
-- --
Capacitive Loading Specs on Output Pins COSC2 OSC2 pin
D101 D102 * Note 1: 2:
CIO CB
All I/O pins and OSC2 (in RC mode) SCL, SDA in I2CTM mode
-- --
-- --
50 400
pF pF
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16CR7X be driven with external clock in RC mode. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin.
3:
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PIC16CR7X
15.3 Timing Parameter Symbology
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impendance) L Low I2CTM only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2CTM specifications only) (I2CTM specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid High-impendance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA Start condition
SU STO
Setup Stop condition
FIGURE 15-2:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin
Legend:
CL VSS
Pin VSS
CL
RL = 464 CL = 50 pF 15 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output
Note: PORTD and PORTE are not implemented on the PIC16CR73/76 devices.
(c) 2007 Microchip Technology Inc.
DS21993C-page 123
PIC16CR7X
FIGURE 15-3: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKOUT 3 3 4 4
TABLE 15-1:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Symbol Characteristic External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) Min DC DC DC DC 0.1 4 5 1000 50 5 250 250 50 5 200 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY Max 1 20 32 4 4 20 200 -- -- -- -- 10,000 250 -- DC Units MHz MHz kHz MHz MHz MHz kHz ns ns ms ns ns ns ms ns Conditions XT osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode XT osc mode HS osc mode LP osc mode RC osc mode XT osc mode HS osc mode LP osc mode TCY = 4/FOSC
FOSC
1
TOSC
External CLKIN Period (Note 1) Oscillator Period (Note 1)
2 3
TCY TosL, TosH
4
Note 1:
500 -- -- ns XT oscillator 2.5 -- -- ms LP oscillator 15 -- -- ns HS oscillator TosR, External Clock in (OSC1) -- -- 25 ns XT oscillator TosF Rise or Fall Time -- -- 50 ns LP oscillator -- -- 15 ns HS oscillator Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time
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PIC16CR7X
FIGURE 15-4: CLKOUT AND I/O TIMING
Q4 OSC1 10 CLKOUT 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 15 New Value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 15-2 for load conditions.
TABLE 15-2:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Symbol TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
CLKOUT AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKOUT CLKOUT rise time CLKOUT fall time CLKOUT to Port out valid Port in valid before CLKOUT Port in hold after CLKOUT OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time Standard (5V) Extended (3V) Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 100 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5TCY + 20 -- -- 255 -- -- -- 40 145 40 145 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckH OSC1 to CLKOUT
19* 20* 21* 22* 23* *
TioV2osH TioR TioF Tinp Trbp
Port input valid to OSC1 (I/O in setup time) Standard (5V) Extended (3V) Standard (5V) Extended (3V)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode, where CLKOUT output is 4 x TOSC.
(c) 2007 Microchip Technology Inc.
DS21993C-page 125
PIC16CR7X
FIGURE 15-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
Note: Refer to Figure 15-2 for load conditions.
FIGURE 15-6:
BROWN-OUT RESET TIMING
VDD
VBOR 35
TABLE 15-3:
Parameter No. 30 31* 32 33* 34 35 *
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impendance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Min 2 7 -- 28 -- 100 Typ -- 18 1024 TOSC 72 -- -- Max -- 33 -- 132 2.1 -- Units s ms -- ms s s VDD VBOR (D005) Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C TOSC = OSC1 period VDD = 5V, -40C to +85C
TmcL TWDT TOST TPWRT TIOZ TBOR
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16CR7X
FIGURE 15-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
40 42
41
RC0/T1OSO/T1CKI
45
46
47 TMR0 or TMR1 Note: Refer to Figure 15-2 for load conditions.
48
TABLE 15-4:
Param No. 40* 41* 42* Symbol Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5TCY + 20 15 25 30 50 0.5TCY + 20 15 25 30 50 Greater of: 30 or TCY + 40 N Greater of: 50 or TCY + 40 N 60 100 DC 2 TOSC -- -- -- -- -- -- 200 7 TOSC ns ns kHz -- Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Conditions Must also meet parameter 42 Must also meet parameter 42
45*
Tt1H
T1CKI High Time Synchronous, Prescaler = 1 Synchronous, Standard(5V) Prescaler = 2,4,8 Extended(3V) Asynchronous Standard(5V) Extended(3V)
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
46*
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1 Synchronous, Standard(5V) Prescaler = 2,4,8 Extended(3V) Asynchronous Standard(5V) Extended(3V) Standard(5V)
Must also meet parameter 47
47*
Tt1P
T1CKI Input Period
Synchronous
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
Extended(3V)
Asynchronous Ft1 48
Standard(5V) Extended(3V)
Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS21993C-page 127
PIC16CR7X
FIGURE 15-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)
RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 52 51
RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 15-2 for load conditions. 54
TABLE 15-5:
Param Symbol No. 50* TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)
Characteristic CCP1 and CCP2 No Prescaler input low time Min 0.5TCY + 20 10 20 0.5TCY + 20 10 20 3TCY + 40 N -- -- -- -- Extended(3V) Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
Standard(5V) With Prescaler Extended(3V) Standard(5V) With Prescaler Extended(3V)
51*
TccH
CCP1 and CCP2 No Prescaler input high time
52* 53* 54* *
TccP TccR TccF
CCP1 and CCP2 input period CCP1 and CCP2 output rise time Standard(5V) CCP1 and CCP2 output fall time Standard(5V) Extended(3V)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16CR7X
FIGURE 15-9:
RE2/CS
PARALLEL SLAVE PORT TIMING (PIC16CR74/77 DEVICES ONLY)
RE0/RD
RE1/WR
65 RD7:RD0 62 63 Note: Refer to Figure 15-2 for load conditions.
64
TABLE 15-6:
PARALLEL SLAVE PORT REQUIREMENTS (PIC16CR74/77 DEVICES ONLY)
Characteristic Min Typ Max Units 20 25 20 35 -- -- 10 -- -- -- -- -- -- -- -- -- -- -- 80 90 30 ns ns ns ns ns ns ns Extended range only Conditions
Parameter Symbol No. 62
TdtV2wrH Data in valid before WR or CS (setup time)
Extended range only
63*
TwrH2dtI
WR or CS to data in invalid (hold time)
Standard(5V) Extended(3V)
64
TrdL2dtV RD and CS to data out valid
65 *
TrdH2dtI
RD or CS to data out invalid
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS21993C-page 129
PIC16CR7X
FIGURE 15-10:
SS 70 SCK (CKP = 0) 71 72
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 15-2 for load conditions. Bit 6 - - - -1
Bit 6 - - - - - -1
LSb
LSb In
FIGURE 15-11:
SS
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
Bit 6 - - - - - -1
LSb
SDI
MSb In 74
Bit 6 - - - -1
LSb In
Note: Refer to Figure 15-2 for load conditions.
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PIC16CR7X
FIGURE 15-12:
SS 70 SCK (CKP = 0) 71 72 83
SPI SLAVE MODE TIMING (CKE = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 15-2 for load conditions. Bit 6 - - - -1
Bit 6 - - - - - -1
LSb 77 LSb In
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
Bit 6 - - - - - -1
LSb 77
SDI
MSb In 74
Bit 6 - - - -1
LSb In
Note: Refer to Figure 15-2 for load conditions.
(c) 2007 Microchip Technology Inc.
DS21993C-page 131
PIC16CR7X
TABLE 15-7:
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83* *
SPI MODE REQUIREMENTS
Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impendance SCK output rise time (Master mode) Standard(5V) Extended(3V) Standard(5V) Extended(3V) Standard(F) Extended(LF) Min TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- Tcy -- 1.5TCY + 40 Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max Units Conditions -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF
SCK output fall time (Master mode)
TscH2doV, SDO data output valid after TscL2doV SCK edge
TdoV2scH, SDO data output setup to SCK edge TdoV2scL TssL2doV SDO data output valid after SS edge TscH2ssH, SS after SCK edge TscL2ssH
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 15-14:
I2CTM BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
Start Condition Note: Refer to Figure 15-2 for load conditions.
Stop Condition
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PIC16CR7X
TABLE 15-8:
Param No. 90* 91* 92* 93 *
I2CTM BUS START/STOP BITS REQUIREMENTS
Characteristic Start condition Setup time Start condition Hold time Stop condition Setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Typ -- -- -- -- -- -- -- -- Max Units -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated Start condition After this period, the first clock pulse is generated
Symbol TSU:STA THD:STA TSU:STO
THD:STO Stop condition Hold time
These parameters are characterized but not tested.
FIGURE 15-15:
I2CTM BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 110 109 SDA Out Note: Refer to Figure 15-2 for load conditions. 109
(c) 2007 Microchip Technology Inc.
DS21993C-page 133
PIC16CR7X
TABLE 15-9:
Param. No. 100*
I2CTM BUS DATA REQUIREMENTS
Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1CB -- 20 + 0.1CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10-400 pF Only relevant for Repeated Start condition After this period the first clock pulse is generated CB is specified to be from 10-400 pF s s Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz Units s s Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz
Symbol THIGH
101*
TLOW
Clock low time
100 kHz mode 400 kHz mode SSP Module
102*
TR
SDA and SCL rise time SDA and SCL fall time Start condition setup time
100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
103*
TF
90*
TSU:STA
91* 106* 107* 92* 109* 110*
THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF
Start condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time Stop condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode
CB * Note 1: 2:
Bus capacitive loading
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released.
DS21993C-page 134
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PIC16CR7X
FIGURE 15-16:
RC6/TX/CK pin RC7/RX/DT pin 120 122 Note: Refer to Figure 15-2 for load conditions.
USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
121 121
TABLE 15-10: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Symbol TckH2dtV Characteristic SYNC XMIT (MASTER & Standard(5V) SLAVE) Clock high to data out valid Extended(3V) Clock out rise time and fall Standard(5V) time (Master mode) Extended(3V) Data out rise time and fall time Standard(5V) Extended(3V) Min Typ Max Units Conditions
-- -- -- -- -- --
-- -- -- -- -- --
80 100 45 50 45 50
ns ns ns ns ns ns
121 122
Tckrf Tdtrf
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 15-17:
RC6/TX/CK pin RC7/RX/DT pin
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 15-2 for load conditions.
TABLE 15-11: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Parameter No. 125 126 Symbol TdtV2ckL TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time) Min Typ Max Units Conditions
15 15
-- --
-- --
ns ns
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
(c) 2007 Microchip Technology Inc.
DS21993C-page 135
PIC16CR7X
TABLE 15-12: A/D CONVERTER CHARACTERISTICS:PIC16CR7X (INDUSTRIAL, EXTENDED)
Param No. A01 A02 A03 A04 A05 A06 A10 A20 A25 A30 A40 Sym NR EABS EIL EDL EFS EOFF -- VREF VAIN ZAIN IAD Characteristic Resolution Total absolute error Integral linearity error Differential linearity error Full scale error Offset error Monotonicity (Note 3) Reference voltage Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) Min -- -- -- -- -- -- -- 2.5 2.2 VSS - 0.3 -- -- Typ -- -- -- -- -- -- guaranteed -- -- -- -- 180 Max 8 bits < 1 < 1 < 1 < 1 < 1 -- 5.5 5.5 VREF + 0.3 10.0 -- Units bit Conditions VREF = VDD = 5.12V, VSS VAIN VREF
LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF LSb VREF = VDD = 5.12V, VSS VAIN VREF -- V V V k A Average current consumption when A/D is on (Note 1). During VAIN acquisition. During A/D Conversion cycle. VSS VAIN VREF -40C to +125C 0C to +125C
A50
IREF
VREF input current (Note 2)
N/A --
-- --
5 500
A A
* Note 1: 2: 3:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from the RA3 pin or the VDD pin, whichever is selected as a reference input. The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS21993C-page 136
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 15-18: A/D CONVERSION TIMING
1 TCY (TOSC/2)(1) 131 130 A/D CLK 132 BSF ADCON0, GO 134 Q4
A/D DATA
7
6
5
4
3
2
1
0
ADRES
OLD_DATA
NEW_DATA
ADIF GO Sampling Stopped DONE
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 15-13: A/D CONVERSION REQUIREMENTS
Param Sym No. 130 TAD Characteristic A/D clock period PIC16CR7X PIC16CR7X PIC16CR7X PIC16CR7X 131 132 TCNV Conversion time (not including S/H time) (Note 1) TACQ Acquisition time Min 1.6 2.0 2.0 3.0 9 5* Typ -- -- 4.0 6.0 -- -- Max -- -- 6.0 9.0 9 -- Units s s s s TAD s The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. Conditions TOSC based, VREF 3.0V TOSC based, 2.0V VREF 5.5V A/D RC mode A/D RC mode
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
* Note 1: 2:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. ADRES register may be read on the following TCY cycle. See Section 11.1 "A/D Acquisition Requirements" for minimum conditions.
(c) 2007 Microchip Technology Inc.
DS21993C-page 137
PIC16CR7X
NOTES:
DS21993C-page 138
(c) 2007 Microchip Technology Inc.
PIC16CR7X
16.0
Note:
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
"Typical" represents the mean of the distribution at 25C. "Maximum" or "minimum" represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over the whole temperature range.
FIGURE 16-1:
7 6 5
TYPICAL IDD vs. FOSC OVER VDD (HS MODE)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V 5.0V 4.5V
IDD(mA)
4 3 2 1 0 4
4.0V
3.5V 3.0V 2.5V 2.0V
6 8 10 12 Fosc(MHz) 14 16 18 20
FIGURE 16-2:
8 7 6 5 IDD(mA) 4 3 2 1 0 4
MAXIMUM IDD vs. FOSC OVER VDD (HS MODE)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V 5.0V 4.5V 4.0V
3.5V 3.0V 2.5V 2.0V
6 8 10 12 Fosc(MHz) 14 16 18 20
(c) 2007 Microchip Technology Inc.
DS21993C-page 139
PIC16CR7X
FIGURE 16-3:
1.2
TYPICAL IDD vs. FOSC OVER VDD (XT MODE)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
1
5.5V 5.0V
0.8
4.5V 4.0V
IDD (mA)
0.6
3.5V 3.0V
0.4
2.5V 2.0V
0.2
0 0.5 1 1.5 2 2.5 3 3.5 4
Fosc (MHz)
FIGURE 16-4:
1.4
MAXIMUM IDD vs. FOSC OVER VDD (XT MODE)
1.2
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.5V
5.0V
1
4.5V
IDD(mA)
0.8
4.0V 3.5V 3.0V
0.6
2.5V
0.4
2.0V
0.2
0 0.5 1 1.5 2 2.5 3 3.5 4
Fosc (MHz)
DS21993C-page 140
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-5:
45 40 35
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
TYPICAL IDD VS. FOSC OVER VDD (LP MODE)
5.5V 5.0V
30 IDD (A) 25 20 15 10 5 0 30 40 50 60 Fosc (KHz) 70 80
4.5V 4.0V
2.0V
90
100
FIGURE 16-6:
85
MAXIMUM IDD vs. FOSC OVER VDD (LP MODE)
5.5V
75
65
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
5.0V 4.5V
IDD (A)
55
45
4.0V
35
2.0V
25
15 30 40 50 60 Fosc (KHz) 70 80 90 100
(c) 2007 Microchip Technology Inc.
DS21993C-page 141
PIC16CR7X
FIGURE 16-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25C)
5.0 4.5 4.0 3.5
Operation above 4 MHz is not recommended
10K (F7x)
Freq (MHz) 3.0
10 k
2.5 2.0 1.5 1.0 0.5 0.0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5
100 k
FIGURE 16-8:
AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25C)
2.5
2
Freq (MHz)
1.5
5.1 k
1
10K (F7x) 10 k
0.5
100 k
0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5
DS21993C-page 142
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25C)
1 0.9 0.8 0.7 Freq (MHz) 0.6 0.5 0.4 0.3 0.2 0.1
3.3K
5.1K
10K (F7x) 10K
100K
0 2.5 3 3.5 4 Vdd (V) 4.5 5 5.5
FIGURE 16-10:
100
IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED)
Max 125C
10 Max 85C
IPD (uA)
1
Typ 25C 0.1
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
0.01 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS21993C-page 143
PIC16CR7X
FIGURE 16-11:
1,000
IBOR vs. VDD OVER TEMPERATURE
Max (125C)
Typ (25C) Indeterminant State Device in SLEEP
IDD (A)
Device in RESET 100
Note:
Device current in Reset depends on Oscillator mode, frequency and circuit.
Max (125C)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
Typ (25C)
10 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-12:
100
TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
Max (125C) 10
IWDT (A)
Typ (25C)
1
0.1 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS21993C-page 144
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-13:
50
TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO 125C) 16F77
45
40
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
35 Max (125C) WDT Period (ms) 30
25 Typ (25C)
20
15
Min (-40C)
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-14:
50
AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40C TO 125C)
45
40 125C 35 85C WDT Period (ms) 30 25C 25
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
20 -40C 15
10
5
0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
(c) 2007 Microchip Technology Inc.
DS21993C-page 145
PIC16CR7X
FIGURE 16-15:
5.5 5.0 4.5 4.0 Max 3.5 Typ (25C) VOH (V) 3.0 2.5 Min 2.0 1.5 1.0 0.5 0.0 0 5 10 IOH (-mA) 15 20 25
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO 125C)
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
FIGURE 16-16:
3.5
TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO 125C)
3.0
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
2.5 Max
2.0 VOH (V) Typ (25C) 1.5 Min 1.0
0.5
0.0 0 5 10 IOH (-mA) 15 20 25
DS21993C-page 146
(c) 2007 Microchip Technology Inc.
PIC16CR7X
FIGURE 16-17:
1.0
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO 125C)
0.9 Max (125C) 0.8
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
0.7 Max (85C)
0.6 VOL (V)
0.5 Typ (25C) 0.4
0.3
Min (-40C)
0.2
0.1
0.0 0 5 10 IOL (-mA) 15 20 25
FIGURE 16-18:
3.0
TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO 125C)
Max (125C) 2.5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
2.0
VOL (V)
1.5 Max (85C)
1.0 Typ (25C)
0.5
Min (-40C)
0.0 0 5 10 IOL (-mA) 15 20 25
(c) 2007 Microchip Technology Inc.
DS21993C-page 147
PIC16CR7X
FIGURE 16-19:
1.5
MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO 125C)
1.4
1.3
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
VTH Max (-40C)
1.2
1.1 VTH Typ (25C) VIN (V) 1.0
0.9
VTH Min (125C)
0.8
0.7
0.6
0.5 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
FIGURE 16-20:
4.0
MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO 125C)
3.5
Typical: statistical mean @ 25C Maximum: mean + 3 (-40C to 125C) Minimum: mean - 3 (-40C to 125C)
VIH Max (125C)
3.0
2.5
VIN (V)
VIH Min (-40C)
2.0
VIL Max (-40C)
1.5
1.0
VIL Min (125C)
0.5
0.0 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5
DS21993C-page 148
(c) 2007 Microchip Technology Inc.
PIC16CR7X
17.0
17.1
PACKAGING INFORMATION
Package Marking Information
28-Lead PDIP
XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX XXXXXXXXXXXXXXX YYWWNNN
Example
PICXXFXXXX-I/P e3 0710017
40-Lead PDIP
XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN
Example
PICXXFXXXX-I/P e3 0710017
44-Lead PLCC
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PICXXFXXX /L e3 0710017
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
(c) 2007 Microchip Technology Inc.
DS21993C-page 149
PIC16CR7X
17.1 Package Marking Information (continued)
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
28-Lead SOIC (.300")
XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN
XXFXXX /ML e3 0710017
Example
PICXXFXXXX/SO e3 0710017
28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example PICXXFXXXX -I/SS e3 0710017
44-Lead TQFP
Example
XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN
PICXXFXXXX -I/PT e3 0710017
DS21993C-page 150
(c) 2007 Microchip Technology Inc.
PIC16CR7X
17.2 Package Details
The following sections give the technical details of the packages.
28-Lead Skinny Plastic Dual In-Line (SP) - 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1 E1
1
2
3 D E
A
A2 L c eB
A1
b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .120 .015 .290 .240 1.345 .110 .008 .040 .014 - MIN
INCHES NOM 28 .100 BSC - .135 - .310 .285 1.365 .130 .010 .050 .018 - .200 .150 - .335 .295 1.400 .150 .015 .070 .022 MAX
.430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B
(c) 2007 Microchip Technology Inc.
DS21993C-page 151
PIC16CR7X
40-Lead Plastic Dual In-Line (P) - 600 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
N NOTE 1 E1
123 D
E A A2 L A1 b1 b e
Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing N e A A2 A1 E E1 D L c b1 b eB - .125 .015 .590 .485 1.980 .115 .008 .030 .014 - MIN INCHES NOM 40 .100 BSC - - - - - - - - - - - .250 .195 - .625 .580 2.095 .200 .015 .070 .023 MAX
c eB
.700 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-016B
DS21993C-page 152
(c) 2007 Microchip Technology Inc.
PIC16CR7X
44-Lead Plastic Leaded Chip Carrier (L) - Square [PLCC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1 CH2 x 45
E E1
NOTE 1
N123
CH1 x 45 CH3 x 45 c A A2 b1 b E2 A3 A1
e D2
Units Dimension Limits Number of Pins Pitch Overall Height Contact Height Molded Package to Contact Standoff Corner Chamfer Chamfers Side Chamfer Overall Width Overall Length Molded Package Width Molded Package Length Footprint Width Footprint Length Lead Thickness Upper Lead Width Lower Lead Width N e A A1 A2 A3 CH1 CH2 CH3 E D E1 D1 E2 D2 c b1 b .165 .090 .062 .020 .042 - .042 .685 .685 .650 .650 .582 .582 .0075 .026 .013 MIN
INCHES NOM 44 .050 .172 .105 - - - - - .690 .690 .653 .653 .610 .610 - - - .180 .120 .083 - .048 .020 .056 .695 .695 .656 .656 .638 .638 .0125 .032 MAX
.021 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. Microchip Technology Drawing C04-048B
(c) 2007 Microchip Technology Inc.
DS21993C-page 153
PIC16CR7X
28-Lead Plastic Quad Flat, No Lead Package (ML) - 6x6 mm Body [QFN] with 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D2
EXPOSED PAD
e E E2 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW 2 1 N L K
b
A
A3
A1
Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 3.65 0.23 0.50 0.20 3.65 0.80 0.00 MIN MILLIMETERS NOM 28 0.65 BSC 0.90 0.02 0.20 REF 6.00 BSC 3.70 6.00 BSC 3.70 0.30 0.55 - 4.20 0.35 0.70 - 4.20 1.00 0.05 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-105B
DS21993C-page 154
(c) 2007 Microchip Technology Inc.
PIC16CR7X
28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1 NOTE 1 123 b e

h h c
A
A2
L A1 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer (optional) Foot Length Footprint Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 E E1 D h L L1 c b 0 0.18 0.31 5 5 0.25 0.40 - 2.05 0.10 MIN
MILLMETERS NOM 28 1.27 BSC - - - 10.30 BSC 7.50 BSC 17.90 BSC - - 1.40 REF - - - - - 8 0.33 0.51 15 0.75 1.27 2.65 - 0.30 MAX
15 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-052B
(c) 2007 Microchip Technology Inc.
DS21993C-page 155
PIC16CR7X
28-Lead Plastic Shrink Small Outline (SS) - 5.30 mm Body [SSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D N
E E1
12 NOTE 1
b e
c A A2 L1
Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Lead Thickness Foot Angle Lead Width N e A A2 A1 E E1 D L L1 c b 0.09 0 0.22 - 1.65 0.05 7.40 5.00 9.90 0.55 MIN MILLIMETERS NOM 28 0.65 BSC - 1.75 - 7.80 5.30 10.20 0.75 1.25 REF - 4 - 0.25 8 0.38 2.00 1.85 - 8.20 5.60 10.50 0.95 MAX
A1
L
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B
DS21993C-page 156
(c) 2007 Microchip Technology Inc.
PIC16CR7X
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging
D D1
E e E1
b
N 123
NOTE 1 c
NOTE 2 A
L
A1
L1
A2
Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 E D E1 D1 c b 0.09 0.30 11 11 0 - 0.95 0.05 0.45 MIN
MILLIMETERS NOM 44 0.80 BSC - 1.00 - 0.60 1.00 REF 3.5 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC - 0.37 12 12 0.20 0.45 13 13 7 1.20 1.05 0.15 0.75 MAX
Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B
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NOTES:
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APPENDIX A: REVISION HISTORY
Revision C (January 2007) This revision includes updates to the packaging diagrams. Revision A (March 2006) This is a new data sheet. However, these devices are similar to the PIC16F7X devices found in the PIC16F7X Data Sheet (DS30325B). Revision B (December 2006) Revised 15.1 DC Characteristics Param. No. D005, D020, D021, D021A; 15.2 DC Characteristics Param. No. D070; Table 15-3, Param. No. 30. Replaced Package drawings.
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
DEVICE DIFFERENCES
PIC16CR73 4K 192 3 5 channels, 8 bits no 11 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin QFN PIC16CR74 4K 192 5 8 channels, 8 bits yes 12 40-pin PDIP 44-pin TQFP 44-pin PLCC PIC16CR76 8K 368 3 5 channels, 8 bits no 11 28-pin PDIP 28-pin SOIC 28-pin SSOP 28-pin MLF PIC16CR77 8K 368 5 8 channels, 8 bits yes 12 40-pin PDIP 44-pin TQFP 44-pin PLCC
Difference ROM Program Memory (14-bit words) Data Memory (bytes) I/O Ports A/D Parallel Slave Port Interrupt Sources Packages
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APPENDIX C: CONVERSION CONSIDERATIONS
Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
TABLE C-1:
CONVERSION CONSIDERATIONS
PIC16CR7X 28/40 3 11 or 12 PSP, USART, SSP (SPI, I2CTM Slave) 20 MHz 8-bit 2 4K, 8K ROM 192, 368 bytes None -- PIC16F87X 28/40 3 13 or 14 PSP, USART, SSP (SPI, I2C Master/Slave) 20 MHz 10-bit 2 4K, 8K FLASH (1,000 E/W cycles) 192, 368 bytes 128, 256 bytes In-Circuit Debugger, Low-Voltage Programming PIC16F7X 28/40 3 11 or 12 PSP, USART, SSP (SPI, I2C Slave) 20 MHz 8-bit 2 4K, 8K FLASH (100 E/W cycles, typical) 192, 368 bytes None --
Characteristic Pins Timers Interrupts Communication Frequency A/D CCP Program Memory RAM EEPROM Data Other
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INDEX
A
A/D A/D Conversio Status (GO/DONE Bit) ........................ 83 Acquisition Requirements ........................................... 86 ADCON0 Register....................................................... 83 ADCON1 Register....................................................... 83 ADRES Register ......................................................... 83 Analog Port Pins ......................................... 8, 10, 12, 39 Analog-to-Digital Converter......................................... 83 Associated Registers .................................................. 88 Configuring Analog Port Pins...................................... 87 Configuring the Interrupt ............................................. 85 Configuring the Module............................................... 85 Conversion Clock........................................................ 87 Conversion Requirements ........................................ 137 Conversions ................................................................ 87 Converter Characteristics ......................................... 136 Effects of a RESET ..................................................... 87 Faster Conversion - Lower Resolution Trade-off ....... 87 Internal Sampling Switch (Rss) Impedance ................ 86 Operation During SLEEP ............................................ 87 Source Impedance...................................................... 86 Using the CCP Trigger................................................ 88 Absolute Maximum Ratings .............................................. 117 ACK pulse ..................................................................... 65, 66 ADCON0 Register............................................................... 83 GO/DONE Bit.............................................................. 83 ADCON1 Register............................................................... 83 ADRES Register ................................................................. 83 Analog Port Pins. See A/D Application Notes AN552 (Implementing Wake-up on Key Strokes Using PIC16F7X) ............................................... 33 AN556 (Implementing a Table Read) ......................... 26 AN578 (Use of the SSP Module in the I2C Multi-Master Environment).................................. 59 AN607 (Power-up Trouble Shooting).......................... 94 Assembler MPASM Assembler................................................... 114 PORTE (In I/O Port Mode) ......................................... 37 PWM Mode................................................................. 57 RC Oscillator Mode .................................................... 92 Recommended MCLR Circuit..................................... 94 Reset Circuit ............................................................... 93 SSP (I2C Mode).......................................................... 65 SSP (SPI Mode) ......................................................... 62 Timer0/WDT Prescaler ............................................... 43 Timer1 ........................................................................ 48 Timer2 ........................................................................ 51 USART Receive .............................................................. 76 USART Transmit ........................................................ 74 Watchdog Timer (WDT)............................................ 101 BOR. See Brown-out Reset BRGH bit ............................................................................ 71 Brown-out Reset (BOR).............................. 89, 93, 94, 95, 96
C
C Compilers MPLAB C18.............................................................. 114 MPLAB C30.............................................................. 114 Capture/Compare/PWM (CCP) Associated Registers............................................ 56, 58 Capture Mode............................................................. 55 Prescaler ............................................................ 55 CCP Pin Configuration ......................................... 55, 56 CCP1 RC2/CCP1 Pin................................................ 9, 11 CCP2 RC1/T1OSI/CCP2 Pin .................................... 9, 11 Compare Mode........................................................... 55 Software Interrupt Mode ..................................... 56 Special Trigger Output........................................ 56 Timer1 Mode Selection....................................... 56 Example PWM Frequencies and Resolutions ............ 58 Interaction of Two CCP Modules................................ 53 PWM Duty Cycle ........................................................ 57 PWM Mode................................................................. 57 PWM Period ............................................................... 57 Setup for PWM Operation .......................................... 58 Special Event Trigger and A/D Conversions .............. 56 Timer Resources ........................................................ 53 CCP1 Module ..................................................................... 53 CCP2 Module ..................................................................... 53 CCPR1H Register............................................................... 53 CCPR1L Register ............................................................... 53 CCPxM<3:0> bits................................................................ 54 CCPxX and CCPxY bits...................................................... 54 CKE bit ............................................................................... 60 CKP bit ............................................................................... 61 Code Examples Call of a Subroutine in Page 1 from Page 0 ............... 26 Changing Between Capture Prescalers ..................... 55 Changing Prescaler Assignment to Timer0 ................ 45 Changing Prescaler Assignment to WDT ................... 45 Indirect Addressing..................................................... 27 Initializing PORTA ...................................................... 31 Reading a 16-bit Free-Running Timer ........................ 49 ROM Program Read................................................... 30 Saving STATUS, W, and PCLATH Registers in RAM............................................................. 100 Writing a 16-bit Free-Running Timer .......................... 49 Code Protection .......................................................... 89, 103
B
Banking, Data Memory ....................................................... 13 BF bit................................................................................... 60 Block Diagrams A/D .............................................................................. 85 Analog Input Model ..................................................... 86 Capture Mode Operation ............................................ 55 Compare ..................................................................... 55 Crystal/Ceramic Resonator Operation (HS, XT or LP Osc Configuration) .................................... 91 External Clock Input Operation (HS Osc Configuration)....................................... 91 Interrupt Logic ............................................................. 99 PIC16CR73 and PIC16CR76........................................ 6 PIC16CR74 and PIC16CR77........................................ 7 PORTA RA3:RA0 and RA5 Port Pins .............................. 31 RA4/T0CKI Pin ................................................... 31 PORTB RB3:RB0 Port Pins ............................................. 33 RB7:RB4 Port Pins ............................................. 33 PORTC (Peripheral Output Override) ......................... 35 PORTD (In I/O Port Mode).......................................... 36 PORTD and PORTE (Parallel Slave Port) .................. 40
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Computed GOTO ................................................................ 26 Configuration Bits................................................................ 89 Continuous Receive Enable (CREN Bit) ............................. 70 Conversion Considerations ............................................... 160 Customer Change Notification Service ............................. 167 Customer Notification Service........................................... 167 Customer Support ............................................................. 167 CLRWDT .................................................................. 108 COMF ....................................................................... 108 DECF ........................................................................ 108 DECFSZ ................................................................... 109 GOTO ....................................................................... 109 INCF ......................................................................... 109 INCFSZ..................................................................... 109 IORLW ...................................................................... 109 IORWF...................................................................... 109 RETURN........................................................... 110, 111 RLF ........................................................................... 111 RRF .................................................................. 110, 111 SLEEP .............................................................. 110, 111 SUBLW ............................................................. 110, 111 SUBWF............................................................. 110, 111 SWAPF ..................................................................... 112 XORLW .................................................................... 112 XORWF .................................................................... 112 Summary Table ........................................................ 106 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register................................................................ 21 GIE Bit ........................................................................ 21 INTE Bit ...................................................................... 21 INTF Bit ...................................................................... 21 RBIF Bit ................................................................ 21, 33 TMR0IE Bit ................................................................. 21 Inter-Integrated Circuit (I2C). See I2C Mode Internet Address ............................................................... 167 Interrupt Sources .......................................................... 89, 99 Interrupt-on-Change (RB7:RB4) ................................. 33 RB0/INT Pin, External..................................... 8, 11, 100 TMR0 Overflow......................................................... 100 USART Receive/Transmit Complete .......................... 69 Interrupts Synchronous Serial Port Interrupt............................... 23 Interrupts, Context Saving During..................................... 100 Interrupts, Enable Bits Global Interrupt Enable (GIE Bit) .......................... 21, 99 Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit).. 100 RB0/INT Enable (INTE Bit) ......................................... 21 TMR0 Overflow Enable (TMR0IE Bit)......................... 21 Interrupts, Flag Bits Interrupt-on Change (RB7:RB4) Flag (RBIF Bit) ........ 21 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit)............................................. 21, 33, 100 RB0/INT Flag (INTF Bit) ............................................. 21 TMR0 Overflow Flag (TMR0IF Bit) ........................... 100
D
D/A bit ................................................................................. 60 Data Memory....................................................................... 13 Bank Select (RP1:RP0 Bits) ....................................... 13 General Purpose Registers......................................... 13 Register File Map, PIC16CR74/73.............................. 15 Register File Map, PIC16CR77/76.............................. 14 Special Function Registers ......................................... 16 Data/Address bit (D/A) ........................................................ 60 DC and AC Characteristics Graphs and Tables ................................................... 139 DC Characteristics ............................................................ 119 Development Support ....................................................... 113 Device Differences ............................................................ 159 Device Overview ................................................................... 5 Features ........................................................................ 5 Direct Addressing................................................................ 27
E
Electrical Characteristics................................................... 117 Errata .................................................................................... 4 External Clock Input (RA4/T0CKI). See Timer0 External Interrupt Input (RB0/INT). See Interrupt Sources
F
Firmware Instructions........................................................ 105 FSR Register....................................................................... 27
I
I/O Ports .............................................................................. 31 I2C Mode Addressing .................................................................. 66 Associated Registers .................................................. 68 Master Mode ............................................................... 68 Mode Selection ........................................................... 65 Multi-Master Mode ...................................................... 68 Operation .................................................................... 65 Reception .................................................................... 66 Slave Mode SCL and SDA pins .............................................. 65 Transmission............................................................... 67 ID Locations ...................................................................... 103 INDF Register ..................................................................... 27 Indirect Addressing ............................................................. 27 FSR Register .............................................................. 13 Instruction Format ............................................................. 105 Instruction Set ................................................................... 105 ADDLW ..................................................................... 107 ADDWF ..................................................................... 107 ANDLW ..................................................................... 107 ANDWF ..................................................................... 107 BCF ........................................................................... 107 BSF ........................................................................... 107 BTFSC ...................................................................... 107 BTFSS ...................................................................... 107 CALL ......................................................................... 108 CLRF......................................................................... 108 CLRW ....................................................................... 108
L
Load Conditions................................................................ 123 Loading of PC ..................................................................... 26
M
Master Clear (MCLR)............................................................ 8 MCLR Reset, Normal Operation..................... 93, 95, 96 MCLR Reset, SLEEP...................................... 93, 95, 96 Operation and ESD Protection ................................... 94 MCLR Pin ........................................................................... 10 MCLR/VPP Pin ...................................................................... 8 Memory Organization ......................................................... 13 Data Memory .............................................................. 13 Program Memory ........................................................ 13 Program Memory and Stack Maps ............................. 13 Microchip Internet Web Site.............................................. 167 MPLAB ASM30 Assembler, Linker, Librarian ................... 114 MPLAB ICD 2 In-Circuit Debugger ................................... 115
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MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 115 MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator .................................................... 115 MPLAB Integrated Development Environment Software .. 113 MPLAB PM3 Device Programmer .................................... 115 MPLINK Object Linker/MPLIB Object Librarian ................ 114 TRISA Register........................................................... 31 PORTA Register ................................................................. 31 PORTB ........................................................................... 8, 11 Associated Registers.................................................. 34 PORTB Register......................................................... 33 Pull-up Enable (RBPU Bit).......................................... 20 RB0/INT Edge Select (INTEDG Bit) ........................... 20 RB0/INT Pin, External .................................... 8, 11, 100 RB7:RB4 Interrupt-on-Change ................................. 100 RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) .... 100 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit).............................................. 21, 33, 100 TRISB Register........................................................... 33 PORTB Register ................................................................. 33 PORTC ........................................................................... 9, 11 Associated Registers.................................................. 35 PORTC Register......................................................... 35 RC0/T1OSO/T1CKI Pin.......................................... 9, 11 RC1/T1OSI/CCP2 Pin ............................................ 9, 11 RC2/CCP1 Pin........................................................ 9, 11 RC3/SCK/SCL Pin.................................................. 9, 11 RC4/SDI/SDA Pin................................................... 9, 11 RC5/SDO Pin ......................................................... 9, 11 RC6/TX/CK Pin................................................. 9, 11, 70 RC7/RX/DT Pin .......................................... 9, 11, 70, 71 TRISC Register .......................................................... 35 PORTC Register................................................................. 35 PORTD ............................................................................... 12 Associated Registers.................................................. 36 Parallel Slave Port (PSP) Function............................. 36 PORTD Register......................................................... 36 TRISD Register .......................................................... 36 PORTD Register................................................................. 36 PORTE ............................................................................... 12 Analog Port Pins................................................... 12, 39 Associated Registers.................................................. 39 Input Buffer Full Status (IBF Bit)................................. 38 Input Buffer Overflow (IBOV Bit)................................. 38 PORTE Register......................................................... 37 PSP Mode Select (PSPMODE Bit)....................... 36, 37 RE0/RD/AN5 Pin .................................................. 12, 39 RE1/WR/AN6 Pin ................................................. 12, 39 RE2/CS/AN7 Pin .................................................. 12, 39 TRISE Register........................................................... 37 PORTE Register ................................................................. 37 Postscaler, WDT Assignment (PSA Bit) ................................................. 20 Rate Select (PS2:PS0 Bits) ........................................ 20 Power-down Mode. See SLEEP Power-on Reset (POR)..................................... 89, 93, 95, 96 Oscillator Start-up Timer (OST)............................ 89, 94 POR Status (POR Bit) ................................................ 25 Power Control (PCON) Register................................. 95 Power-down (PD Bit) .................................................. 93 Power-up Timer (PWRT) ...................................... 89, 94 Time-out (TO Bit).................................................. 19, 93 PR2 Register ...................................................................... 51 Prescaler, Timer0 Assignment (PSA Bit) ................................................. 20 Rate Select (PS2:PS0 Bits) ........................................ 20 Program Counter RESET Conditions...................................................... 95 Program Memory ................................................................ 29 Associated Registers.................................................. 30 Interrupt Vector........................................................... 13 Memory and Stack Maps ............................................ 13
O
OPCODE Field Descriptions ............................................. 105 OPTION_REG Register ...................................................... 20 INTEDG Bit ................................................................. 20 PS2:PS0 Bits .............................................................. 20 PSA Bit........................................................................ 20 RBPU Bit..................................................................... 20 T0CS Bit...................................................................... 20 T0SE Bit...................................................................... 20 OSC1/CLKI Pin ............................................................... 8, 10 OSC2/CLKO Pin ............................................................. 8, 10 Oscillator Configuration....................................................... 89 Oscillator Configurations ..................................................... 91 Crystal Oscillator/Ceramic Resonators ....................... 91 HS ......................................................................... 91, 95 LP.......................................................................... 91, 95 RC................................................................... 91, 92, 95 XT ......................................................................... 91, 95 Oscillator, WDT ................................................................. 101
P
P (STOP) bit........................................................................ 60 Packaging ......................................................................... 149 Marking ..................................................................... 149 PDIP Details.............................................................. 151 Paging, Program Memory ................................................... 26 Parallel Slave Port Associated Registers .................................................. 41 Parallel Slave Port (PSP) .............................................. 36, 40 RE0/RD/AN5 Pin................................................... 12, 39 RE1/WR/AN6 Pin.................................................. 12, 39 RE2/CS/AN7 Pin................................................... 12, 39 Select (PSPMODE Bit) ......................................... 36, 37 PCFG0 bit ........................................................................... 84 PCFG1 bit ........................................................................... 84 PCFG2 bit ........................................................................... 84 PCL Register....................................................................... 26 PCLATH Register ............................................................... 26 PCON Register ............................................................. 25, 95 POR Bit ....................................................................... 25 PICSTART Plus Development Programmer ..................... 116 PIE1 Register ...................................................................... 22 PIE2 Register ...................................................................... 24 Pinout Descriptions PIC16CR73/PIC16CR76........................................... 8-9 PIC16CR74/PIC16CR77....................................... 10-12 PIR1 Register...................................................................... 23 PIR2 Register...................................................................... 24 PMADR Register................................................................. 29 PMADRH Register .............................................................. 29 POP .................................................................................... 26 POR. See Power-on Reset PORTA............................................................................ 8, 10 Analog Port Pins ..................................................... 8, 10 Associated Registers .................................................. 32 PORTA Register ......................................................... 31 RA4/T0CKI Pin........................................................ 8, 10 RA5/SS/AN4 Pin ..................................................... 8, 10
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Operation During Code Protect................................... 30 Organization................................................................ 13 Paging ......................................................................... 26 PMADR Register......................................................... 29 PMADRH Register ...................................................... 29 Reading ROM ............................................................. 30 Reading, PMADR Register ......................................... 29 Reading, PMADRH Register....................................... 29 Reading, PMCON1 Register ....................................... 29 Reading, PMDATA Register ....................................... 29 Reading, PMDATH Register ....................................... 29 RESET Vector............................................................. 13 Program Verification.......................................................... 103 Programming, Device Instructions .................................... 105 PUSH .................................................................................. 26 ADRES (A/D Result)................................................... 83 CCP1CON/CCP2CON Register ................................. 54 Configuration Word Register ...................................... 90 Initialization Conditions (table).............................. 96-97 INTCON (Interrupt Control)......................................... 21 INTCON Register........................................................ 21 OPTION_REG ............................................................ 20 OPTION_REG Register........................................ 20, 44 PCON (Power Control) ............................................... 25 PCON Register ........................................................... 25 PIE1 (Peripheral Interrupt Enable 1)........................... 22 PIE1 Register ............................................................. 22 PIE2 (Peripheral Interrupt Enable 2)........................... 24 PIE2 Register ............................................................. 24 PIR1 (Peripheral Interrupt Request 1) ........................ 23 PIR1 Register ............................................................. 23 PIR2 (Peripheral Interrupt Request 2) ........................ 24 PIR2 Register ............................................................. 24 PMCON1 (Program Memory Control 1) Register ....... 29 RCSTA Register ......................................................... 70 Special Function, Summary.................................. 16-18 SSPCON Register ...................................................... 61 SSPSTAT Register ..................................................... 60 STATUS Register ....................................................... 19 T1CON Register ......................................................... 47 T2CON Register ......................................................... 52 TRISE Register........................................................... 38 TXSTA Register.......................................................... 69 RESET .......................................................................... 89, 93 Brown-out Reset (BOR). See Brown-out Reset (BOR) MCLR Reset. See MCLR Power-on Reset (POR). See Power-on Reset (POR) RESET Conditions for All Registers ........................... 96 RESET Conditions for PCON Register....................... 95 RESET Conditions for Program Counter .................... 95 RESET Conditions for STATUS Register ................... 95 Reset WDT Reset. See Watchdog Timer (WDT) Revision History................................................................ 159
R
R/W bit .................................................................... 60, 66, 67 RA0/AN0 Pin ................................................................... 8, 10 RA1/AN1 Pin ................................................................... 8, 10 RA2/AN2 Pin ................................................................... 8, 10 RA3/AN3/VREF Pin.......................................................... 8, 10 RA4/T0CKI Pin................................................................ 8, 10 RA5/SS/AN4 Pin ............................................................. 8, 10 RAM. See Data Memory RB0/INT Pin .................................................................... 8, 11 RB1 Pin ........................................................................... 8, 11 RB2 Pin ........................................................................... 8, 11 RB3 Pin ........................................................................... 8, 11 RB4 Pin ........................................................................... 8, 11 RB5 Pin ........................................................................... 8, 11 RB6 Pin ........................................................................... 8, 11 RB7 Pin ........................................................................... 8, 11 RC0/T1OSO/T1CKI Pin .................................................. 9, 11 RC1/T1OSI/CCP2 Pin..................................................... 9, 11 RC2/CCP1 Pin ................................................................ 9, 11 RC3/SCK/SCL Pin .......................................................... 9, 11 RC4/SDI/SDA Pin ........................................................... 9, 11 RC5/SDO Pin .................................................................. 9, 11 RC6/TX/CK Pin ............................................................... 9, 11 RC7/RX/DT Pin ............................................................... 9, 11 RCSTA Register CREN Bit..................................................................... 70 OERR Bit .................................................................... 70 SPEN Bit ..................................................................... 69 SREN Bit ..................................................................... 70 RD0/PSP0 Pin..................................................................... 12 RD1/PSP1 Pin..................................................................... 12 RD2/PSP2 Pin..................................................................... 12 RD3/PSP3 Pin..................................................................... 12 RD4/PSP4 Pin..................................................................... 12 RD5/PSP5 Pin..................................................................... 12 RD6/PSP6 Pin..................................................................... 12 RD7/PSP7 Pin..................................................................... 12 RE0/RD/AN5 Pin................................................................. 12 RE1/WR/AN6 Pin ................................................................ 12 RE2/CS/AN7 Pin ................................................................. 12 Reader Response ............................................................. 168 Read-Modify-Write Operations.......................................... 105 Receive Overflow Indicator bit (SSPOV)............................. 61 Register File ........................................................................ 13 Registers ADCON0 (A/D Control 0) ............................................ 83 ADCON0 Register....................................................... 83 ADCON1 (A/D Control 1) ............................................ 83 ADCON1 Register....................................................... 84
S
S (START) bit ..................................................................... 60 SCI. See USART SCL..................................................................................... 65 Serial Communication Interface. See USART SLEEP .................................................................. 89, 93, 102 SMP bit ............................................................................... 60 Software Simulator (MPLAB SIM) .................................... 114 Special Features of the CPU .............................................. 89 Special Function Registers ..................................... 16, 16-18 Speed, Operating.................................................................. 1 SPI Mode ............................................................................ 59 Associated Registers .................................................. 64 Serial Clock (SCK pin) ................................................ 59 Serial Data In (SDI pin)............................................... 59 Serial Data Out (SDO pin) .......................................... 59 Slave Select................................................................ 59 SSP Overview RA5/SS/AN4 Pin..................................................... 8, 10 RC3/SCK/SCL Pin .................................................. 9, 11 RC4/SDI/SDA Pin ................................................... 9, 11 RC5/SDO Pin.......................................................... 9, 11 SSP I2C Operation.............................................................. 65 Slave Mode................................................................. 65 SSPEN bit........................................................................... 61
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SSPIF bit ............................................................................. 23 SSPM<3:0> bits .................................................................. 61 SSPOV bit ........................................................................... 61 Stack ................................................................................... 26 Overflows .................................................................... 26 Underflow.................................................................... 26 STATUS Register DC Bit.......................................................................... 19 IRP Bit......................................................................... 19 PD Bit.......................................................................... 93 TO Bit.................................................................... 19, 93 Z Bit............................................................................. 19 Synchronous Serial Port Enable bit (SSPEN)..................... 61 Synchronous Serial Port Interrupt bit (SSPIF) .................... 23 Synchronous Serial Port Mode Select bits (SSPM<3:0>) ... 61 Synchronous Serial Port. See SSP I2C Bus Start/Stop Bits ............................................. 132 I2C Reception (7-bit Address)..................................... 67 I2C Transmission (7-bit Address) ............................... 67 Parallel Slave Port .................................................... 129 Parallel Slave Port Read Waveforms ......................... 41 Parallel Slave Port Write Waveforms ......................... 41 Power-up Timer ........................................................ 126 PWM Output ............................................................... 57 RESET...................................................................... 126 Slow Rise Time (MCLR Tied to VDD Through RC Network)......................................... 98 SPI Master Mode (CKE = 0, SMP = 0) ..................... 130 SPI Master Mode (CKE = 1, SMP = 1) ..................... 130 SPI Mode (Master Mode) ........................................... 63 SPI Mode (Slave Mode with CKE = 0)........................ 63 SPI Mode (Slave Mode with CKE = 1)........................ 64 SPI Slave Mode (CKE = 0) ....................................... 131 SPI Slave Mode (CKE = 1) ....................................... 131 Start-up Timer........................................................... 126 Time-out Sequence on Power-up (MCLR Not Tied to VDD) Case 1 ................................................................ 98 Case 2 ................................................................ 98 Time-out Sequence on Power-up (MCLR Tied to VDD Through RC Network)......... 97 Timer0 ...................................................................... 127 Timer1 ...................................................................... 127 USART Asynchronous Master Transmission ............. 74 USART Asynchronous Master Transmission (Back to Back) ................................................... 75 USART Asynchronous Reception .............................. 76 USART Synchronous Receive (Master/Slave) ......... 135 USART Synchronous Reception (Master Mode, SREN) ........................................ 80 USART Synchronous Transmission ........................... 79 USART Synchronous Transmission (Master/Slave) .................................................. 135 USART Synchronous Transmission (Through TXEN) ................................................. 79 Wake-up from Sleep via Interrupt............................. 103 Watchdog Timer ....................................................... 126 Timing Parameter Symbology .......................................... 123 Timing Requirements Capture/Compare/PWM (CCP1 and CCP2)............. 128 CLKOUT and I/O ...................................................... 125 External Clock .......................................................... 124 I2C Bus Data............................................................. 134 I2C Bus Start/Stop Bits............................................. 133 Parallel Slave Port .................................................... 129 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset . 126 SPI Mode.................................................................. 132 Timer0 and Timer1 External Clock ........................... 127 USART Synchronous Receive ................................. 135 USART Synchronous Transmission ......................... 135 TMR1CS bit ........................................................................ 47 TMR1ON bit........................................................................ 47 TMR2ON bit........................................................................ 52 TOUTPS<3:0> bits ............................................................. 52 TRISA Register................................................................... 31 TRISB Register................................................................... 33 TRISC Register................................................................... 35 TRISD Register................................................................... 36
T
T1CKPS0 bit ....................................................................... 47 T1CKPS1 bit ....................................................................... 47 T1OSCEN bit ...................................................................... 47 T1SYNC bit ......................................................................... 47 T2CKPS0 bit ....................................................................... 52 T2CKPS1 bit ....................................................................... 52 TAD ....................................................................................... 87 Time-out Sequence............................................................. 94 Timer0 ................................................................................. 43 Associated Registers .................................................. 45 Clock Source Edge Select (T0SE Bit)......................... 20 Clock Source Select (T0CS Bit).................................. 20 External Clock............................................................. 44 Interrupt....................................................................... 43 Overflow Enable (TMR0IE Bit).................................... 21 Overflow Flag (TMR0IF Bit) ...................................... 100 Overflow Interrupt ..................................................... 100 Prescaler..................................................................... 45 RA4/T0CKI Pin, External Clock .............................. 8, 10 T0CKI.......................................................................... 44 Timer1 ................................................................................. 47 Associated Registers .................................................. 50 Asynchronous Counter Mode ..................................... 49 Capacitor Selection..................................................... 50 Counter Operation ...................................................... 48 Operation in Timer Mode ............................................ 48 Oscillator ..................................................................... 50 Prescaler..................................................................... 50 RC0/T1OSO/T1CKI Pin .......................................... 9, 11 RC1/T1OSI/CCP2 Pin............................................. 9, 11 Resetting of Timer1 Registers .................................... 50 Resetting Timer1 using a CCP Trigger Output ........... 50 Synchronized Counter Mode ...................................... 48 TMR1H Register ......................................................... 49 TMR1L Register.......................................................... 49 Timer2 ................................................................................. 51 Associated Registers .................................................. 52 Output ......................................................................... 51 Postscaler ................................................................... 51 Prescaler..................................................................... 51 Prescaler and Postscaler ............................................ 51 Timing Diagrams A/D Conversion......................................................... 137 Brown-out Reset ....................................................... 126 Capture/Compare/PWM (CCP1 and CCP2) ............. 128 CLKOUT and I/O....................................................... 125 External Clock........................................................... 124 I2C Bus Data ............................................................. 133
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TRISE Register ................................................................... 37 IBF Bit ......................................................................... 38 IBOV Bit ...................................................................... 38 PSPMODE Bit ....................................................... 36, 37 TXSTA Register SYNC Bit ..................................................................... 69 TRMT Bit ..................................................................... 69 TX9 Bit ........................................................................ 69 TX9D Bit...................................................................... 69 TXEN Bit ..................................................................... 69
W
Wake-up from SLEEP......................................................... 89 Interrupts .............................................................. 95, 96 MCLR Reset ............................................................... 96 WDT Reset ................................................................. 96 Wake-up from Sleep ......................................................... 102 Wake-up Using Interrupts ................................................. 102 Watchdog Timer (WDT).............................................. 89, 101 Associated Registers ................................................ 101 Enable (WDTE Bit) ................................................... 101 Postscaler. See Postscaler, WDT Programming Considerations ................................... 101 RC Oscillator............................................................. 101 Time-out Period ........................................................ 101 WDT Reset, Normal Operation....................... 93, 95, 96 WDT Reset, SLEEP........................................ 93, 95, 96 WCOL bit ............................................................................ 61 Write Collision Detect bit (WCOL) ...................................... 61 WWW Address ................................................................. 167 WWW, On-Line Support ....................................................... 4
U
UA ....................................................................................... 60 Universal Synchronous Asynchronous Receiver Transmitter. See USART Update Address bit, UA....................................................... 60 USART ................................................................................ 69 Asynchronous Mode ................................................... 73 Asynchronous Receiver .............................................. 75 Asynchronous Reception ............................................ 76 Associated Registers .......................................... 77 Asynchronous Transmission Associated Registers .......................................... 75 Asynchronous Transmitter .......................................... 73 Baud Rate Generator (BRG)....................................... 71 Baud Rate Formula............................................. 71 Baud Rates, Asynchronous Mode (BRGH = 0) .. 72 Baud Rates, Asynchronous Mode (BRGH = 1) .. 72 Sampling ............................................................. 71 Mode Select (SYNC Bit) ............................................. 69 Overrun Error (OERR Bit) ........................................... 70 RC6/TX/CK Pin ....................................................... 9, 11 RC7/RX/DT Pin ....................................................... 9, 11 Serial Port Enable (SPEN Bit)..................................... 69 Single Receive Enable (SREN Bit) ............................. 70 Synchronous Master Mode ......................................... 78 Synchronous Master Reception .................................. 80 Associated Registers .......................................... 81 Synchronous Master Transmission............................. 78 Associated Registers .......................................... 79 Synchronous Slave Mode ........................................... 81 Synchronous Slave Reception .................................... 82 Associated Registers .......................................... 82 Synchronous Slave Transmission............................... 81 Associated Registers .......................................... 82 Transmit Data, 9th Bit (TX9D)..................................... 69 Transmit Enable (TXEN Bit)........................................ 69 Transmit Enable, Nine-bit (TX9 Bit) ............................ 69 Transmit Shift Register Status (TRMT Bit).................. 69 User Code ......................................................................... 103
DS21993C-page 166
(c) 2007 Microchip Technology Inc.
PIC16CR7X
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
(c) 2007 Microchip Technology Inc.
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DS21993C-page 167
PIC16CR7X
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16CR7X Questions: 1. What are the best features of this document? Y N Literature Number: DS21993C FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21993C-page 168
Advance Information
(c) 2007 Microchip Technology Inc.
PIC16CR7X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
Device:
PIC16CR73 PIC16CR74 PIC16CR76 PIC16CR77 I E PT L SO SP P = -40C to +85C = -40C to+125C = = = = = (Industrial) (Extended)
Temperature Range: Package:
TQFP (Thin Quad Flatpack) PLCC SOIC Skinny Plastic DIP PDIP
Note1: 2:
Pattern:
QTP, SQTP, Code or Special Requirements (blank otherwise)
F = Standard Voltage Range LF = Wide Voltage Range T = in tape and reel PLCC, and TQFP packages only.
(c) 2007 Microchip Technology Inc.
Advance Information
DS21993C-page 169
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
12/08/06
DS21993C-page 170
(c) 2007 Microchip Technology Inc.

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